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| fujitsu semiconductor controller manual f 2 mc-16lx 16-bit microcontroller MB90580 series hardware manual
iii preface thank you for selecting fujitsu semiconductor devices. the fujitsu MB90580 series has been developed as one general-application version of the f 2 mc ? *16lx series of original 16-bit one-chip microcontrollers for asic (application specific ic) applications. this manual describes the functions and operations of the MB90580 series, and is intended for use by engineers actually designing products using these semiconductors. please be sure to read it carefully. *: f 2 mc is an abbreviation for fujitsu flexible microcontroller, and is a registered trademark of fujitsu. this document is organized as follows. chapter 1 overview this section presents an overview of MB90580 series features and functions. chapter 2 cpu this section describes the functions of the f 2 mc-16lx series cpu. chapter 3 memory this section describes the functions of the f 2 mc-16lx series memory. chapter 4 clock and reset this section describes the functions of the MB90580 series clocks and resets. chapter 5 watchdog timer, time base timer, and watch timer function this section describes the functions and operation of the MB90580 series watchdog timer, timebase timer and watch timer function. chapter 6 low power control circuit this section describes the MB90580 series low power control circuits (cpu intermittent operation function, oscillator stabilization wait time, pll clock multiplier function). chapter 7 interrupt this section describes the functions of each MB90580 each interrupt and interrupt source. chapter 8 parallel ports this section describes the functions of the MB90580 series parallel port. chapter 9 dtp/external interrupt this section describes the function and operation of the MB90580 series dtp and external interrupts. chapter 10 delay interrupt module this section describes the functions and operation of the MB90580 series delay interrupt module. chapter 11 iv chapter 12 communication prescaler this section describes the MB90580 series communication prescaler. chapter 13 uart this section describes the function and operation of the MB90580 uart. chapter 14 ie bus this section describes the functions and operation of the MB90580 series ie bus. chapter 15 8/16-bit ppg this section describes the functions and operation of the MB90580 series 8/16-bit ppg. chapter 16 16-bit reload timer (with event count function) this section describes the functions and operation of the MB90580 series 16-bit reload timer. chapter 17 a/d converterr this section describes the functions and oeration of the MB90580 series a/d converter. chapter 18 d/a converter this section describes the functions and oeration of the MB90580 series d/a converter chapter 19 pulse width counter (pwc) timer this section describes the functions and oeration of the MB90580 series pulse width counter (pwc) timer. chapter 20 clock monitor function this section describes the functions of the MB90580 series clock monitor function. chapter 21 16-bit i/o timers this section describes the functions and operation of the MB90580 series 16-bit i/o timers which consists of 16-bit free-run timer, 2 output compare regsiters and 4 input capture registers. chapter 22 rom correction module this section describes the function and operation of the MB90580 series rom correction module. chapter 23 rom mirroring module this section describes the function of the MB90580 series rom mirroriing module. appendix a i/o map the appendix a provides i/o maps, and low power mode status transition charts. appendix b instruction the appendix b describes addressing in the f 2 mc ? *-16lx series, and provides instruction lists and instruction maps. appendix c programming the flash memory on the mb90f584 the appendix c provides programming method of the flash memory on the mb90f584. MB90580 series v contents chapter 1 overview .......................................................................................................... .................................1 1.1 features ................................................................................................................. .........................1 1.2 product lineup ........................................................................................................... .....................3 1.3 block diagram ............................................................................................................ .....................4 1.4 pin assignment ........................................................................................................... ....................5 1.4.1 sqfp-100 pin assignment ................................................................................................ ....5 1.4.1 qfp-100 pin assignment ................................................................................................. .....6 1.5 pin functions ............................................................................................................ ......................7 1.6 handling the device ...................................................................................................... ................14 chapter 2 cpu ................................................................................................................ ..................................15 2.1 cpu ...................................................................................................................... .........................15 2.1.1 memory space ........................................................................................................... ..........16 2.1.2 registers .............................................................................................................. ...............20 2.1.3 prefix codes ........................................................................................................... ..............28 chapter 3 memory ............................................................................................................. ...............................31 3.1 memory access modes ...................................................................................................... ...........31 3.1.1 mode pins .............................................................................................................. ..............32 3.1.2 mode data .............................................................................................................. ..............33 3.1.3 bus mode ............................................................................................................... .............34 3.2 external memory access ................................................................................................... ............36 3.2.1 block diagram .......................................................................................................... ............36 3.2.2 registers and register details ......................................................................................... ....37 3.2.1 operations ............................................................................................................. ..............42 chapter 4 clock and reset .................................................................................................... ..........................47 4.1 clock generator .......................................................................................................... ..................47 4.2 reset causes ............................................................................................................. ...................48 4.3 operation after reset release ............................................................................................ ............50 chapter 5 watchdog timer, timebase timer, and watch timer functions ...............................................51 5.1 outline .................................................................................................................. .........................51 5.2 block diagram ............................................................................................................ ...................52 5.3 registers and register details ........................................................................................... .............53 5.3.1 wdtc (watch-dog timer control register) .......................................................................54 5.3.2 tbtc (time base timer control register) .........................................................................56 5.3.3 watch timer control register (wtc) ..................................................................................57 5.4 operation ................................................................................................................ ......................59 5.4.1 watch-dog timer ........................................................................................................ ........59 5.4.2 time base timer ........................................................................................................ .........60 5.4.3 watch timer ............................................................................................................ ............60 chapter 6 low power control circuit .......................................................................................... ...................61 6.1 outline .................................................................................................................. .........................61 6.2 block diagram ............................................................................................................ ...................62 6.3 registers and register details ........................................................................................... .............63 6.3.1 lpmcr (low power mode control register) ........................................................................63 6.3.2 ckscr (clock selection register) ....................................................................................... 65 6.4 operations ............................................................................................................... ......................67 6.4.1 sleep mode ............................................................................................................. ............68 6.4.2 pseudo-watch mode ...................................................................................................... ......68 vi MB90580 series 6.4.3 watch mode ............................................................................................................. ...........69 6.4.4 stop mode .............................................................................................................. .............69 6.4.5 hardware standby mode .................................................................................................. ...70 6.4.6 cpu intermittent operation function .................................................................................... .70 6.4.7 setting the main clock oscillation stabilization waiting period ..............................................71 6.4.8 switching the machine clock ............................................................................................ ...71 6.4.9 state transition ....................................................................................................... ..............73 chapter 7 interrupt .......................................................................................................... .................................81 7.1 outline .................................................................................................................. .........................81 7.2 causes of interrupt ...................................................................................................... ..................82 7.3 interrupt vector ......................................................................................................... ....................83 7.4 hardware interrupt ....................................................................................................... .................84 7.4.1 overview ............................................................................................................... ...............84 7.4.2 structure .............................................................................................................. ................84 7.4.3 operation .............................................................................................................. ...............84 7.4.4 hardware interrupt ocurrence when internal resource is being accessed ......................87 7.4.5 interrupt inhibit instruction .......................................................................................... .........87 7.4.6 multiple interrupts .................................................................................................... ............87 7.4.7 register saving in stack upon interrupt .............................................................................87 7.4.8 precaution in using hardware interrupt ..............................................................................87 7.5 software interrupt ....................................................................................................... ...................88 7.5.1 overview ............................................................................................................... ...............88 7.5.2 structure .............................................................................................................. ................88 7.5.3 operation .............................................................................................................. ...............89 7.5.4 others ................................................................................................................. .................89 7.6 extended intelligent i/o service (ei2os) ................................................................................. ......90 7.6.1 overview ............................................................................................................... ...............90 7.6.2 structure .............................................................................................................. ................91 7.6.3 operation .............................................................................................................. ...............97 7.6.4 ei2os execution time ................................................................................................... .....99 7.7 exceptions ............................................................................................................... ....................100 7.7.1 exception due to execution of an undefined instruction ....................................................100 chapter 8 parallel ports ..................................................................................................... ............................101 8.1 outline .................................................................................................................. .......................101 8.2 block diagram ............................................................................................................ .................102 8.3 registers and register details ........................................................................................... ...........103 8.3.1 port data register ..................................................................................................... ..........104 8.3.2 port direction registers ............................................................................................... ........105 8.3.3 output pin register .................................................................................................... .........106 8.3.4 input resistor register ................................................................................................ .........106 8.3.5 analogue input enable register ........................................................................................1 07 8.3.6 low noise output select register .....................................................................................10 7 chapter 9 dtp/external interrupt ............................................................................................. .....................109 9.1 outline .................................................................................................................. .......................109 9.2 block diagram ............................................................................................................ .................109 9.3 registers and register details ........................................................................................... .........110 9.3.1 interrupt/dtp enable register (enir: enable interrupt request register) ...........................110 9.3.2 interrupt/dtp cause register (eirr: external interrupt request register) ..........................111 9.3.3 request level setting register (elvr: external level register) ...........................................111 MB90580 series vii 9.4 operations ............................................................................................................... ....................112 9.4.1 external interrupts .................................................................................................... .........112 9.4.2 dtp operation .......................................................................................................... .........113 9.4.3 switching between external interrupt and dtp requests ...................................................114 9.5 notes on use ............................................................................................................. ..................115 9.5.1 conditions on the externally connected peripheral when dtp is used .............................115 9.5.2 recovery from standby .................................................................................................. ....115 9.5.3 external interrupt/dtp operation procedure ......................................................................115 9.5.4 external interrupt request level ....................................................................................... ...115 chapter 10 delayed interrupt generation module ............................................................................... ........117 10.1 outline ................................................................................................................. ......................117 10.2 block diagram ........................................................................................................... ................117 10.3 registers and register details .......................................................................................... ........117 10.4 operations .............................................................................................................. ...................118 10.4.1 delayed interrupt occurrence .......................................................................................... 118 10.5 notes on operation ...................................................................................................... ..............118 10.5.1 delayed interrupt request lock ........................................................................................ .118 chapter 11 communication prescaler ........................................................................................... ...............119 11.1 outline ................................................................................................................. ......................119 11.2 block diagram ........................................................................................................... ................119 11.3 register and register details ........................................................................................... .........120 11.3.1 clock division control registers .....................................................................................1 20 11.4 operations .............................................................................................................. ...................121 chapter 12 uart .............................................................................................................. ..............................123 12.1 outline ................................................................................................................. ......................123 12.2 block diagram ........................................................................................................... ................124 12.3 register and register details ........................................................................................... .........125 12.3.1 serial mode register (smr0/1/2/3/4) ..............................................................................126 12.3.2 serial control register (scr0/1/2/3/4) ...........................................................................128 12.3.3 serial input data register (sidr0/1/2/3/4)/ serial ouput data register (sodr0/1/2/3/4) 130 12.3.4 serial status register (ssr0/1/2/3/4) .............................................................................130 12.4 operations .............................................................................................................. ...................132 12.4.1 operation modes ....................................................................................................... ......132 12.4.2 uart clock selection .................................................................................................. ....132 12.4.3 asynchronous mode ..................................................................................................... ...134 12.4.4 clk synchronous mode .................................................................................................. 135 12.4.5 interrupt occurrence and flag set timing ..........................................................................137 12.4.6 i2os (intelligent i/o service) ........................................................................................ ...139 12.4.7 notes on use ......................................................................................................... .........139 12.4.8 application ........................................................................................................... ............139 chapter 13 ie bus ............................................................................................................ ...............................141 13.1 outline ................................................................................................................. ......................141 13.2 block diagram ........................................................................................................... ................142 13.3 registers and register details .......................................................................................... ........143 13.3.1 command register upper byte (cmrh) ...........................................................................146 13.3.2 command register lower byte (cmrl) ............................................................................148 13.3.3 unit address register (mawh, mawl) ............................................................................150 13.3.4 slave address register (sawh, sawl) ..........................................................................150 13.3.5 mutliaddress, control bit set register (dcwr) .................................................................151 viii MB90580 series 13.3.6 telegraph length set register (dewr) ............................................................................152 13.3.7 status register upper byte (strh) ..................................................................................153 13.3.8 status register lower byte (strl) ...................................................................................15 5 13.3.9 lock read register (lrrh, lrrl) ...................................................................................157 13.3.10 master address read register (marh, marl) ...............................................................158 13.3.11 multiaddress, control bit read register (dcrr) ..............................................................159 13.3.12 telegraph length read register (derr) .........................................................................160 13.3.13 read data buffer (rdb) ............................................................................................... ..161 13.3.14 write data buffer (wdb) .............................................................................................. ..162 13.4 iebus communication protocol ............................................................................................ ....163 13.4.1 overview .............................................................................................................. ............163 13.4.2 determining bus mastership (arbitration) ........................................................................164 13.4.3 communication mode .................................................................................................... ..164 13.4.4 communication address ................................................................................................. .165 13.4.5 multiaddress communication ...........................................................................................1 65 13.4.6 transfer protocol ..................................................................................................... ........166 13.4.7 transmit data ......................................................................................................... ..........170 13.4.8 bit format ............................................................................................................ .............173 13.5 operation ............................................................................................................... ...................174 13.5.1 iebus control ......................................................................................................... ..........174 13.5.2 communication status .................................................................................................. ...177 13.5.3 program flow example for iebus controller .....................................................................179 13.5.4 timing diagram of multiple frame transmission ............................................................186 13.5.5 timing diaram of transmission data when an error is generated .....................................188 chapter 14 8/16-bit ppg ...................................................................................................... ..........................191 14.1 outline ................................................................................................................. ......................191 14.2 block diagram ........................................................................................................... ................192 14.3 registers and register details .......................................................................................... ........194 14.3.1 ppg0 operation mode control register (ppgc0) ............................................................195 14.3.2 ppg1 operation mode control register (ppgc1) .............................................................197 14.3.3 ppg0, 1 output pin control register (ppgoe) .................................................................199 14.3.4 reload register (prll/prlh ) ........................................................................................20 0 14.4 operations .............................................................................................................. ...................201 chapter 15 16-bit reload timer (with event count function) ................................................................... 207 15.1 outline ................................................................................................................. ......................207 15.2 block diagram ........................................................................................................... ................208 15.3 registers and register details .......................................................................................... ........209 15.3.1 timer control status register (tmcsr) ............................................................................210 15.3.2 tmr (16-bit timer register)/tmrlr (16-bit reload register) .............................................213 15.4 operation ............................................................................................................... ...................214 15.4.1 internal clock operation .............................................................................................. .....214 15.4.2 underflow operation ................................................................................................... .....215 15.4.3 input pin functions (for internal clock mode) ....................................................................216 15.4.4 external event counter ................................................................................................ .....216 15.4.5 output pin functions .................................................................................................. .......217 15.4.6 intelligent i/o service (i2os) function and interrupts .......................................................217 15.4.7 counter operation state ............................................................................................... ....218 chapter 16 a/d converter ..................................................................................................... .........................219 16.1 outline ................................................................................................................. ......................219 16.2 block diagram ........................................................................................................... ................220 MB90580 series ix 16.3 registers and register details .......................................................................................... ........221 16.3.1 control status registers (adcs1 and adcs2) ................................................................222 16.3.2 adcr1 and adcr0 (data registers) ..............................................................................226 16.4 operations .............................................................................................................. ...................228 16.5 notes on use ............................................................................................................ .................234 16.5.1 other considerations ................................................................................................. .....234 chapter 17 d/a converter ..................................................................................................... .........................235 17.1 outline ................................................................................................................. ......................235 17.2 block diagram ........................................................................................................... ................236 17.3 registers and register details .......................................................................................... ........237 17.3.1 dat0/1 ( d/a data register) ........................................................................................... ..238 17.3.2 dacr0/1 ( d/a control register) ......................................................................................2 38 17.4 operations .............................................................................................................. ...................239 chapter 18 pulse width counter (pwc) timer ................................................................................... .........241 18.1 outline ................................................................................................................. ......................241 18.2 block diagram ........................................................................................................... ................242 18.3 regiaters and register details .......................................................................................... ........243 18.3.1 pwc control status register (pwcsr) ............................................................................244 18.3.2 pwc data buffer register (pwcr) ...................................................................................249 18.3.3 divide ratio control register (divr) ..............................................................................250 18.3.4 pwc noise cancelling register (rncr) ...........................................................................251 18.4 operations .............................................................................................................. ...................252 18.5 precautions ............................................................................................................. ..................265 chapter 19 clock monitor function ............................................................................................ ..................267 19.1 outline ................................................................................................................. ......................267 19.2 block diagram ........................................................................................................... ................267 19.3 registers and register details .......................................................................................... ........268 19.3.1 clock output enable register (clkr) ...............................................................................268 chapter 20 16-bit i/o timer .................................................................................................. .........................269 20.1 outline ................................................................................................................. ......................269 20.2 block diagram ........................................................................................................... ................271 20.2.1 overall block diagram of 16-bit i/o timer .......................................................................271 20.2.2 block diagram of 16-bit free-run timer .............................................................................272 20.2.3 block diagram of output comparison .............................................................................272 20.2.4 block diagram of input capture ......................................................................................27 3 20.3 registers and register details .......................................................................................... ........274 20.3.1 16-bit free-run timer ................................................................................................. ........274 20.3.2 output comparison ..................................................................................................... .....278 20.3.3 input capture ......................................................................................................... ...........282 20.4 operations .............................................................................................................. ...................285 20.4.1 16-bit free-run timer ................................................................................................. ........285 20.4.2 16-bit output compare ................................................................................................. .....286 20.4.3 16-bit input capture .................................................................................................. ........287 20.5 timing .................................................................................................................. .....................288 20.5.1 16-bit free-run timer count timing .................................................................................... .288 20.5.2 output compare timing ................................................................................................. ...289 20.5.3 input capture input timing ............................................................................................ ....290 chapter 21 rom correction module ............................................................................................. ................291 21.1 outline ................................................................................................................. ......................291 x MB90580 series 21.2 block diagram ........................................................................................................... ................291 21.3 registers and register details .......................................................................................... ........292 21.3.1 program address detect register 0/1 (padr0/padr1) ................................................292 21.3.2 program address detect control status register (pacsr) ............................................293 21.4 operations .............................................................................................................. ...................294 21.5 application example ..................................................................................................... .............295 chapter 22 rom mirroring module .............................................................................................. .................299 22.1 outline ................................................................................................................. ......................299 22.2 block diagram ........................................................................................................... ................299 22.3 registers and register details .......................................................................................... ........300 22.3.1 rom mirror function select register ..............................................................................300 appendix a i/o map............................................................................................................ ............................ 303 a.1 i/o map .................................................................................................................. .....................303 appendix b instructions ....................................................................................................... ......................... 309 b.1 addressing ............................................................................................................... ...................309 b.1.1 effective address field ................................................................................................ .......309 b.1.2 addressing details ..................................................................................................... .......310 b.2 instruction set .......................................................................................................... ...................314 b.2.1 f 2 mc-16lx instruction set (351 instructions) ..................................................................320 b.3 instruction map .......................................................................................................... .................334 b.3.1 basic page map ......................................................................................................... .......336 appendix c the flash memory in the mb90f583................................................................................... ..... 357 c.1 outline .................................................................................................................. ......................357 c.2 sector structure of 1m bit flash memory .................................................................................. .358 c.3 flash control register (fmcs) ............................................................................................ ......359 c.4 automatic algorithm initiation method .................................................................................... ....361 c.5 automatic algorithm execution status ..................................................................................... ..362 c.5.1 data polling flag (dq7) ................................................................................................ .....363 c.5.2 toggle bit flag (dq6) .................................................................................................. .......364 c.5.3 exceeded timing limits flag (dq5) .....................................................................................3 65 c.5.4 sector erase timer flag (dq3) .......................................................................................... .366 c.6 notes on flash memory program/erase ....................................................................................36 7 c.6.1 read/reset status ...................................................................................................... ........367 c.6.2 data programming ....................................................................................................... .....368 c.6.3 chip erase ............................................................................................................. ...........370 c.6.4 sector erase ........................................................................................................... ..........370 c.6.5 suspend sector erase ................................................................................................... ...372 c.6.6 resume sector erase .................................................................................................... ...372 MB90580 series xi figures chapter 1 overview ........................................................................................................... .................................1 figure 1.3a block diagram of MB90580 series ................................................................................... . 4 figure 1.4a pin assignment of MB90580 (lqfp-100).......................................................................... 5 figure 1.4b pin assignment of MB90580 (qfp-100)............................................................................ 6 figure 1.6a using external clock .............................................................................................. ........... 14 figure 1.6b connection of power pins .......................................................................................... ...... 14 chapter 2 cpu ................................................................................................................ ..................................15 figure 2.1.1a sample relationship between f2mc-16lx system and memory map .......................... 16 figure 2.1.1b sample linear addressing........................................................................................ ...... 17 figure 2.1.1c physical addresses of each space ................................................................................ 18 figure 2.1.1d sample allocation of multi-byte data in memory ........................................................... 19 figure 2.1.1e execution of movw a, 080ffffh ............................................................................... 19 figure 2.1.2a special registers............................................................................................... ............. 20 figure 2.1.2b general-purpose registers ....................................................................................... ..... 21 figure 2.1.2c program counter................................................................................................. ........... 21 figure 2.1.2d 32-bit data transfer ............................................................................................ ............ 22 figure 2.1.2e al-ah transfer .................................................................................................. ............ 22 figure 2.1.2f stack manipulation instruction and stack pointer ........................................................... 23 figure 2.1.2g ps structure .................................................................................................... .............. 24 figure 2.1.2h condition code register configuration........................................................................... . 24 figure 2.1.2i register bank pointer ........................................................................................... .......... 25 figure 2.1.2j interrupt level register........................................................................................ ............. 25 figure 2.1.2k generating a physical address in direct addressing mode............................................ 27 figure 2.1.3a interrupt disable instruction ................................................................................... ........ 29 figure 2.1.3b interrupt disable instructions and prefix codes.............................................................. 30 figure 2.1.3c consecutive prefix codes ........................................................................................ ...... 30 chapter 3 memory ............................................................................................................. ...............................31 figure 3.1.3a access areas and physical addresses in each bus mode............................................. 34 figure 3.2.1a external bus pin control circuit ................................................................................ ...... 36 figure 3.2.1a external memory access timing chart ........................................................................... 4 2 figure 3.2.1b external memory access timing chart ........................................................................... 4 3 figure 3.2.1c ready timing chart .............................................................................................. .......... 44 figure 3.2.1d hold timing ..................................................................................................... ............... 45 chapter 4 clock and reset .................................................................................................... ..........................47 figure 4.1a clock generator circuit block diagram ............................................................................. . 47 figure 4.2a reset cause bit block diagram ..................................................................................... .... 49 figure 4.2b wdtc (watch-dog timer control register)......................................................................... 4 9 figure 4.3a source and destination of reset vector and mode data.................................................... 50 xii MB90580 series chapter 5 watchdog timer, timebase timer, and watch timer functions ...............................................51 figure 5.2a watchdog timer, timebase timer, and watch timer block diagram ............................. 52 figure 5.4.1a watch-dog timer operation....................................................................................... ..... 59 chapter 6 low power control circuit .......................................................................................... ...................61 figure 6.2a low-power consumption control circuit and clock generator ........................................... 62 figure 6.4.8a clock selection state transition diagram (1) ............................................................... 72 figure 6.4.8b clock selection state transition diagram (2) ............................................................... 73 figure 6.4.9a low power consumption mode transition diagram a ................................................. 77 figure 6.4.9b low power consumption mode transition diagram b ................................................. 78 figure 6.4.9c low power consumption mode transition diagram c ................................................. 79 figure 6.4.9d low power consumption mode transition diagram d ................................................. 80 chapter 7 interrupt .......................................................................................................... .................................81 figure 7.4.3a occurrence and release of hardware interrupt ............................................................. 85 figure 7.4.3b hardware interrupt operation flow ............................................................................... .. 86 figure 7.4.7a registers saved in stack ........................................................................................ ....... 87 figure 7.5.3a occurrence and release of software interrupt .............................................................. 89 figure 7.6.1a outline of extended intelligent i/o service .................................................................... 90 figure 7.6.2a extended intelligent i/o service descriptor configuration ............................................ 94 figure 7.6.3a ei2os operation flow ............................................................................................ ........ 97 figure 7.6.3b ei2os use flow .................................................................................................. ........... 98 chapter 8 parallel ports ..................................................................................................... ............................101 figure 8.2a block diagram of i/o port ......................................................................................... ...... 102 figure 8.2b block diagram of input resistor register.......................................................................... 102 figure 8.2c block diagram of output pin register .............................................................................. 102 figure 8.3a registers of parallel ports ....................................................................................... ...... 103 chapter 9 dtp/external interrupt ............................................................................................. .....................109 figure 9.2a block diagram of dtp/external interrupt ....................................................................... 109 figure 9.4.1a external interrupt.............................................................................................. ........... 112 figure 9.4.2a timing to cancel the external interrupt at the end of dtp operation........................... 113 figure 9.4.2b sample interface to the external peripheral ................................................................ 113 figure 9.4.3a switching between external interrupt and dtp requests ............................................ 114 figure 9.5.4a clearing the cause hold circuit upon level set............................................................. 115 figure 9.5.4b interrupt cause and interrupt request to the interrupt controller while interrupts are enabled ......................................................................................................... ............... 115 chapter 10 delayed interrupt generation module ............................................................................... ........117 figure 10.2a block diagram of delayed interrupt generation module .............................................. 117 figure 10.4.1a delayed interrupt issuance ..................................................................................... .. 118 chapter 11 communication prescaler ........................................................................................... ...............119 figure 11.2a block diagram of communication prescaler ................................................................ 119 MB90580 series xiii chapter 12 uart .............................................................................................................. ..............................123 figure 12.2a block diagram of uart............................................................................................ .... 124 figure 12.3a registers of uart ................................................................................................ ....... 125 figure 12.4.3a transfer data format (modes 0 and 1) ...................................................................... 134 figure 12.4.4a transfer data format (mode 2) .................................................................................. 135 figure 12.4.5a timing to set pe, ore, fre, and rdrf (mode 0) .................................................. 137 figure 12.4.5b timing to set ore, fre, and rdrf (mode 1) ......................................................... 137 figure 12.4.5c timing to set ore and rdrf (mode 2).................................................................... 138 figure 12.4.5d timing to set tdre (modes 0 and 1)........................................................................ 138 figure 12.4.5e timing to set tdre (mode 2) ................................................................................... 138 figure 12.4.8a sample system configuration in mode 1 ................................................................... 139 figure 12.4.8b flow chart of communication in mode 1.................................................................... 140 chapter 13 ie bus ............................................................................................................ ...............................141 figure 13.2a block diagram of ie bus .......................................................................................... .... 142 figure 13.3a registers of ie bus (1/3)....................................................................................... ..... 143 figure 13.3b registers of ie bus (2/3)........................................................................................ ..... 144 figure 13.3c registers of ie bus (3/3) ........................................................................................ ..... 145 figure 13.5.4a when setting 1 on wdbc (master side of master transmission) ............................ 186 figure 13.5.4b when setting 0 on wdbc (master side of master transmission) ............................ 187 figure 13.5.5a error happened on the slave side when master transmission.................................. 188 figure 13.5.5b error happened on the master side when master transmission................................ 189 chapter 14 8/16-bit ppg ...................................................................................................... ..........................191 figure 14.2a 8-bit ppg ch0 block diagram ...................................................................................... . 192 figure 14.2b 8-bit ppg ch1 block diagram ...................................................................................... . 193 figure 14.3a registers of 8/16-bit ppg ........................................................................................ .... 194 figure 14.4a ppg output operation, output waveform ...................................................................... 202 figure 14.4b 8+8 ppg output operation waveform........................................................................... 203 figure 14.4c write timing chart ............................................................................................... .......... 205 figure 14.4d prl write operation block diagram .............................................................................. 2 05 chapter 15 16-bit reload timer (with event count function) ................................................................... 207 figure 15.2a block diagram of 16-bit reload timer......................................................................... 208 figure 15.3a registers of 16-bit reload timer ................................................................................. 209 figure 15.3.1a timer control status register.................................................................................. . 210 figure 15.3.2a 16-bit timer register and 16-bit reload register .................................................... 213 figure 15.4.1a counter activation and operation ............................................................................. 2 14 figure 15.4.2a underflow operation ............................................................................................ ..... 215 figure 15.4.3a trigger input operation ........................................................................................ ..... 216 figure 15.4.3b gate input operation ........................................................................................... ..... 216 figure 15.4.5a output pin functions (1) ....................................................................................... .... 217 figure 15.4.5b output pin functions (2) ....................................................................................... .... 217 xiv MB90580 series figure 15.4.7a counter state transitions ...................................................................................... ... 218 chapter 16 a/d converter ..................................................................................................... .........................219 figure 16.2a block diagram of a/d converter................................................................................... 220 figure 16.3a registers of a/d converter ....................................................................................... ... 221 figure 16.3.1a control status registers ....................................................................................... .... 222 figure 16.3.2a data registers ................................................................................................. ......... 226 figure 16.4a flow chart of a/d conversion ..................................................................................... . 229 figure 16.4b flow chart of data protection function ....................................................................... 233 chapter 17 d/a converter ..................................................................................................... .........................235 figure 17.2a block diagram of d/a cobverter .................................................................................. 236 figure 17.3a register of d/a converter ........................................................................................ .... 237 chapter 18 pulse width counter (pwc) timer ................................................................................... .........241 figure 18.2a lock diagram of pulse width counter timer ................................................................ 242 figure 18.3a register of pulse width counter timer ....................................................................... 243 figure 18.4a timer operation (single-shot mode) ........................................................................... 252 figure 18.4b timer operation (reload mode) .................................................................................. 2 52 figure 18.4c pulse width count operation (single-shot count mode, "h" width count mode) ...... 253 figure 18.4d pulse width count operation (continuous count mode, "h" width count mode) ...... 253 figure 18.4e operation mode selection ......................................................................................... .. 255 figure 18.4f flowchart of timer mode operation ............................................................................. 25 9 figure 18.4g flowchart of operation in pulse width count mode .................................................... 264 chapter 19 clock monitor function ............................................................................................ ..................267 figure 19.2a block diagram of clock monitor function ................................................................... 267 figure 19.3a registers of clock monitor function ............................................................................ 2 68 chapter 20 16-bit i/o timer .................................................................................................. .........................269 figure 20.2.1a overall block diagram of 16-bit i/o timer ................................................................. 271 figure 20.2.2a block diagram of 16-bit free-run timer....................................................................... 2 72 figure 20.2.3a block diagram of output comparison ....................................................................... 272 figure 20.2.4a block diagram of input capture ................................................................................ 273 figure 20.3.1a registers of 16-bit free-run timer ............................................................................. . 274 figure 20.3.2a registers of output comparsion ................................................................................ 278 figure 20.3.3a register of input capture ...................................................................................... ..... 282 chapter 21 rom correction module ............................................................................................. ................291 figure 21.2a block diagram of rom correction module .................................................................. 291 figure 21.3a registers of rom correction module .......................................................................... 292 figure 21.5a system structure example ........................................................................................ . 295 figure 21.5b rom correction processing example ......................................................................... 296 figure 21.5c rom correction processing flow diagram ................................................................. 297 chapter 22 rom mirroring module .............................................................................................. .................299 MB90580 series xv figure 22.2a block diagram of rom mirroring module .................................................................... 299 figure 22.3a register of rom mirroring module .............................................................................. 30 0 figure 22.3b memory in single chip mode ....................................................................................... 301 figure 22.3c memory in internal rom external bus mode............................................................... 301 appendix a i/o map ........................................................................................................... .............................303 appendix b instructions ...................................................................................................... ..........................309 fig. b.1.2a register list configuration ...................................................................................... ........312 fig. b.3a structure of f 2 mc-16lx instruction map........................................................................... 334 fig. b.3b correspondence between actual instructions and the instruction maps ........................... 335 appendix c the flash memory in the mb90f583 .................................................................................. ......357 figure c.2a sector structure of 1m bit flash memory....................................................................... 35 8 figure c.3a timing of rdyint and rdy.......................................................................................... 360 figure c.6.2a example flowchart of progamming the flash memory .................................................369 figure c.6.4a example flowchart of erasing flash memory ...............................................................371 xvi MB90580 series MB90580 series xvii tables chapter 1 overview ........................................................................................................... .................................1 table 1.2a MB90580 series product lineup ....................................................................................3 table 1.5a pin functions (1/4) (stbc: with standby control) ......................................................7 table 1.5b pin functions (2/4) ............................................................................................... ..........8 table 1.5c pin functions (3/4) ............................................................................................... ..........9 table 1.5d pin functions (4/4) ............................................................................................... ........10 table 1.5e i/o circuit format (1) ............................................................................................ ........11 table 1.5f i/o circuit format (2) ............................................................................................ ........12 table 1.5g i/o circuit format (3) ............................................................................................ ........13 chapter 2 cpu ................................................................................................................ ..................................15 table 2.1.1a default space ................................................................................................... ...........18 table 2.1.2a levels indicated by the interrupt level mask (ilm) register .........................................25 table 2.1.2b register functions ............................................................................................. .........26 table 2.1.2c relationship between registers .................................................................................. .26 table 2.1.3a bank select prefix .............................................................................................. .........28 chapter 3 memory ............................................................................................................. ...............................31 table 3.1a memory access mode ................................................................................................ 31 table 3.1.1a mode pins and modes ............................................................................................. ...32 table 3.1.3a sample recommended setting of mode pins and mode data .....................................35 table 3.1.3b modes and related external pin operations .................................................................35 table 3.2.0a selecting the high-order address bit output control ....................................................39 chapter 4 clock and reset .................................................................................................... ..........................47 table 4.2a reset causes ...................................................................................................... ........48 table 4.2b reset cause bits .................................................................................................. .......49 chapter 5 watchdog timer, timebase timer, and watch timer functions ...............................................51 table 5.3.1a reset cause registers ........................................................................................... ......54 table 5.3.1b watchdog timer interval selection bits ......................................................................55 table 5.3.2a selecting the time base timer interval .........................................................................5 6 table 5.3.3a watch timer interval selection .................................................................................. .58 chapter 6 low power control circuit .......................................................................................... ...................61 table 6.3.1a cg bit setting .................................................................................................. ...........64 table 6.3.2a ws bit settings ................................................................................................. ..........65 table 6.3.2b cs bit settings ................................................................................................. ...........66 table 6.4a low power consumption mode operating statuses ..................................................67 table 6.4.9a list of transition conditions ................................................................................... ....74 chapter 7 interrupt .......................................................................................................... .................................81 table 7.2a interrupt causes, interrupt vectors, and interrupt control registers .............................82 xviii MB90580 series table 7.3a MB90580 interrupt assignment table (1/2) ..................................................................83 table 7.4.3a compensation values for interrupt processing cycle count ........................................86 table 7.6.2a ics bits, channel numbers, and descriptor addresses ...............................................92 table 7.6.2b s bits and end conditions ....................................................................................... .....92 table 7.6.2c interrupt level setting bits and interrupt levels ............................................................93 table 7.6.4a execution time when the extended i2os continues ...................................................99 table 7.6.4b data transfer compensation values for extended i2os execution time ......................99 chapter 8 parallel ports ..................................................................................................... ............................101 chapter 9 dtp/external interrupt ............................................................................................. .....................109 chapter 10 delayed interrupt generation module ............................................................................... ........117 chapter 11 communication prescaler ........................................................................................... ...............119 chapter 12 uart .............................................................................................................. ..............................123 table 12.4.1a uart operation modes ........................................................................................... .132 table 12.4.2a baud rate (f indicates the machine clock.) ................................................................132 table 12.4.2b baud rates and reload values ................................................................................... 133 chapter 13 ie bus ............................................................................................................ ...............................141 table 13.3.1a transmission mode .............................................................................................. ....146 table 13.3.1b setting for gotm and gots ...................................................................................147 table 13.3.2a interval for the occurrence of data transmit interrupt ................................................148 table 13.3.2b interval for the occurrence of data transmit interrupt ................................................148 table 13.3.2c interval for the occurrence of data transmit interrupt ................................................148 table 13.3.2d internal clock frequency ....................................................................................... .....149 table 13.3.5a control bits setting ........................................................................................... .........151 table 13.3.6a number of transmit data bytes setting ......................................................................152 table 13.3.8a status flag .................................................................................................... .............156 table 13.3.13a time required for next data receive after receive buffer full interrupt occurred ......161 table 13.3.14a data write time after wdb empty interrupt ...............................................................162 table 13.4.1a iebus transfer rates ........................................................................................... .......163 table 13.4.3a transfer rate and maximum number of transfer byte in each communication mode 164 table 13.4.6a number of transmit data bytes setting ......................................................................167 table 13.4.7a control bits setting ........................................................................................... .........170 table 13.4.7b the control command that can be executed by a locked slave unit .........................170 table 13.4.7c meaning of slave status ........................................................................................ ...171 table 13.5.1a time required to write transmit data to wdb after transmit interrupt has occurred .175 table 13.5.2a meaning of status code st3-0 for master, slave transmit ........................................177 table 13.5.2b meaning of status code st3-0 for master receive ....................................................177 table 13.5.2c meaning of status code st3-0 for slave receive .......................................................178 table 13.5.2d meaning of status code st3-0 for multiaddress receive ...........................................178 chapter 14 8/16-bit ppg ...................................................................................................... ..........................191 MB90580 series xix table 14.4a reload operation and pulse output ...........................................................................201 chapter 15 16-bit reload timer (with event count function) ................................................................... 207 chapter 16 a/d converter ..................................................................................................... .........................219 chapter 17 d/a converter ..................................................................................................... .........................235 table 17.4a theoretical values of d/a converter output voltages ................................................239 chapter 18 pulse width counter (pwc) timer ................................................................................... .........241 table 18.4a count clock selection ............................................................................................ ..254 table 18.4b start and stop bit functions ..................................................................................... 256 table 18.4c operating state indicator bit functions ....................................................................256 table 18.4d count clock and period ........................................................................................... .258 table 18.4e count input pin selection (n = 3 to 0) .......................................................................260 table 18.4f count modes ...................................................................................................... ......261 table 18.4g pulse width count range ........................................................................................26 3 chapter 19 clock monitor function ............................................................................................ ..................267 chapter 20 16-bit i/o timer .................................................................................................. .........................269 chapter 21 rom correction module ............................................................................................. ................291 chapter 22 rom mirroring module .............................................................................................. .................299 appendix a i/o map ........................................................................................................... .............................303 table a.1a i/o map ........................................................................................................... ................303 appendix b instructions ...................................................................................................... ..........................309 table b.1.1a effective address field ......................................................................................... ....309 table b.2a explanation of items in table of instructions ............................................................314 table b.2b explanation of symbols in table of instructions .......................................................316 table b.2c effective address fields .......................................................................................... .317 table b.2d number of execution cycles for each form of addressing ......................................318 table b.2e compensation values for number of cycles used to calculate number of actual cycles ............................................................................................................318 table b.2f compensation values for number of cycles used to calculate number of program fetch cycles ..............................................................................................319 table b.2.1a transfer instructions (byte) (41 instructions) ............................................................320 table b.2.1b transfer instructions (word/long-word) (38 instructions) .......................................321 table b.2.1c addition and subtraction instructions (byte/word/long-word) (42 instructions) .....322 table b.2.1d increment and decrement instructions (byte/word/long-word) (12 instructions) ...323 table b.2.1e compare instructions (byte/word/long-word) (11 instructions) ..............................323 table b.2.1f unsigned multiplication and division instructions (word/long-word) (11 instructions) 324 table b.2.1g signed multiplication and division instructions (word/long-word) (11 instructions) 325 table b.2.1h logical 1 instructions (byte/word) (39 instructions) .................................................326 table b.2.1i logical 2 instructions (long-word) (6 instructions) ..................................................327 table b.2.1j sign inversion instructions (byte/word) (6 instructions) ...........................................327 xx MB90580 series table b.2.1k normalize instruction (long-word) (1 instruction) ....................................................327 table b.2.1l shift instructions (byte/word/long-word) (18 instructions) .....................................328 table b.2.1m branch 1 instructions (31 instructions) .....................................................................329 table b.2.1n branch 2 instructions (19 instructions) .....................................................................330 table b.2.1o other control instructions (byte/word/long-word) (36 instructions) .......................331 table b.2.1p bit manipulation instructions (22 instructions) ..........................................................332 table b.2.1q accumulator manipulation instructions (byte/word) (6 instructions) ........................333 table b.2.1r string instructions (10 instructions) ..........................................................................3 33 table b.3.1a basic page map .................................................................................................. ......336 table b.3.1b bit manipulation instruction map (first byte = 6 ch) ................................................337 table b.3.1c character string manipulation instruction map (first byte = 6eh) ...........................338 table b.3.1d two-byte instruction map (first byte = 6fh) ............................................................339 table b.3.1e ea instructions 1 (first byte = 70h) ........................................................................340 table b.3.1f ea instructions 22 (first byte = 71h) ......................................................................341 table b.3.1g ea instructions 3 (first byte = 72h) ........................................................................34 2 table b.3.1h ea instructions 4 (first byte = 73h) ........................................................................34 3 table b.3.1i ea instructions 5 (first byte = 74h) ........................................................................34 4 table b.3.1j ea instructions 6 (first byte = 75h) ........................................................................34 5 table b.3.1k ea instructions 7 (first byte = 76h) ........................................................................34 6 table b.3.1l ea instructions 8 (first byte = 77h) ........................................................................34 7 table b.3.1m ea instructions 9 (first byte = 78h) .......................................................................34 8 table b.3.1n movea rwi, ea (first byte = 79h) ..........................................................................349 table b.3.1o mov ri, ea (first byte = 7ah) ..................................................................................3 50 table b.3.1p movw rwi, ea (first byte = 7bh) ...........................................................................351 table b.3.1q mov ea, ri (first byte = 7ch) ..................................................................................3 52 table b.3.1r movw ea, rwi (first byte = 7dh) ...........................................................................353 table b.3.1s ch ri, ea (first byte = 7eh) .................................................................................... .354 table b.3.1t xchw rwi, ea (first byte = 7fh) ............................................................................355 appendix c the flash memory in the mb90f583 .................................................................................. ......357 table c.4a command sequence definitions ....................................................................................36 1 table c.5a hardware sequence flags bit assignment ......................................................................362 table c.5b hardware sequence flag ............................................................................................ ...362 table c.5.1a status change of data polling flag (dq7) .................................................................363 table c.5.2a status change of toggle bit flag (dq6) .....................................................................364 table c.5.3a status change of exceeded timing limits flag (dq5) ................................................365 table c.5.4a status change of sector erase tomer flag (dq3) .....................................................366 chapter 1: overview the MB90580 series 16-bit microcontrollers are designed for applications that require high-speed real-time processing. these microcontrollers feature functions that are suitable for controlling car audio and electronic appliances. 1.1 features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can e selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz, 4 mhz to 16 mhz). minimum instruction execution time of 83.3ns (at oscillation of 4 mhz, three times the pll clock, operation at vcc of 5.0 v) ? cpu addressing space of 16 mbytes internal addressing of 24-bit external accessing can be performed by selecting 8/16-bit bus width (external bus mode) ? instruction set optimized for controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) high code efficiency enhanced precision calculation realized by the 32-bit accumulatorinstruction set designed for high level language (c) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? enhanced execution speed 4-byte instruction queue ? enhanced interrupt function 8 levels, 32 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os) ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) timebase timer mode (mode in which other than oscillation and timebase timer are stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode hardware stand-by mode ? i/o port maximum of 77 ports ? ie bus :1 channels small scale two-line serial bus interface for automotive and general industrial application maximium transfer rate is 27 kbps 1.1 features 2 chapter 1: overview MB90580 series ? timers 18-bit timebase counter/watchdog timer: 1 channel watch-dog timer : 1 channel 15-bit watch timer : 1 channel 8/16-bit ppg timer: 8-bit 2 channels or 16-bit 1 channel 16-bit re-load timer: 3 channels 16-bit pwc timer (with noise filter) : 1 channel 16-bit i/o timer (16-bit free-run timer): 1 channel ? input capture (icu) : 4 channels generates an interrupt request by latching a 16-bit free-run timer counter value upon detection of an edge input to the pin. ? output compare (ocu) : 2 channels generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free-run timer counter value and the compare setting value. ? uart : 5 channels with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used. ? tp/external interrupt circuit : 8 channels a module for starting extended intelligent i/o service (ei 2 os) and generating an external interrupt triggered by an external input. ? delayed interrupt generation module generates an interrupt request for switching tasks. ? clock monitor function output the clock to i/o port (dividing the machine clock by 2 to 2 8 . ? rom correction module replace the internal rom code by small external circuit. ? rom mirroring module used to increase the coding efficiency. ? 10-bit a/d converter : 8 channels 10-bit resolution can be selectively used. starting by an external trigger input. ? 8-bit d/a converter : 2 independent channels 8-bit resolution. r-2r typet. ? package lqfp-100, qfp-100 ? process cmos technology 1.2 product lineup MB90580 series chapter 1: overview 3 1.2 product lineup internal configuration table 1.2a lists the product lineup of the MB90580 series. all products are functionally identical except for rom and ram sizes. note: mb90v580 is the evaluation device of MB90580 series, that has no internal rom incorporated. however it has 6kbytes of internal ram and the internal resources. the package of mb90v580 is pga-256c-a02. table 1.2a MB90580 series product lineup mb90v580 mb90583 mb90f583 rom size ______ mask rom 128 kbytes flash rom 128 kbytes ram size 6kbyte 6kbyte 6kbyte others 1.3 block diagram 4 chapter 1: overview MB90580 series 1.3 block diagram figure 1.3a block diagram of MB90580 series x0,x1 rstx hstx dvrh dvss ram rom 4 8 note: p00 to p07 (8 channels): with registers that can be used as input pull-up resistors p10 to p17 (8 channels): with registers that can be used as input pull-up resistors p60 to p65 (6 channels): with registers that can be used as input pull-up resistors p40 to p47 (8 channels): with registers that can be used as open drains f 2 mc-16lx bus clock control d/a converter (8 bits) interrupt controller 8+8 ppg 16-bit pwc timer clock monitor dtp/external interrupt circuit x 1 channel 16-bit reload timer x 3 channels iebus? x0a,x1a noise filter x 2 channels p00-07/ad00-07 p10-17/ad08-15 p20-27/a16-23 p30/ale p31/rdx p32/wrlx p33/wrhx p34/hrq p35/hakx p36/rdy p37/clk cmos i/o port 0, 1, 2, 3 p47 cmos i/o port 4 and 5 cmos i/o port 7 p80/irq0 - p87/irq7 cmos i/o port 8 2 tx rx cmos i/o port 6 cmos i/o port 9 p97/pot cmos i/o port a pa0-2 3 8 16-bit icu x 4 channels 16-bit ocu x 2 channels 16-bit free-run timer i/o timer 8 8 rom correction rom mirroring external bus interface p50/an0/sin3 p51/an1/sot3 p52/an2/sck3 p53/an3 p54/an4/sin4 p55/an5/sot4 p56/an6/sck4 p57/an7 cpu f 2 mc-16lx series core p43/sin1 p44/sot1 p45/sck1 p40/sin0 p41/sot0 p42/sck0 p46/adtg6 p74/da01 p73/da00 p72 p71 p64/ppg1 p63/ppg0 p65/ckot p62/sck2 p61/sot2 p60/sin2 p96/pwc p93/tot0/in3 p94/tot1/out0 p95/tot2/out1 p90/tin0/in0 p91/tin1/in1 p92/tin2/in2 delayed interrupt generator timebase timer avcc avrh,avrl avss a/d converter 8 (10 bits) 2 communication uart prescaler x 5 x 5 channels controller reset circuit (watch-dog timer) hardware standby circuit vss x 3, vcc x 2, md0-2 and c other pins 1.4 pin assig n me n t mb90 5 8 0 seri e s c h ap t e r 1: overview 5 1. 4 p in assignment 1.4.1 lqfp-100 pin assignment figure 1.4a pin assignment of MB90580 (lqfp-100) p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rdx v s s p32/wrlx p33/wrhx p34/hr0 p35/ha k x p36/rdy p37/clk p4 0 / s in0 p41 / s o t0 p 42/ s ck0 p4 3 / s in1 p44 / s o t1 vcc p 45/ s ck1 p 4 6/ a dtg p47 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rstx pa1 pa0 p97/pot p96/pwc p95/ t ot2/ o ut1 p94/ t ot1/ o ut0 p93/ t ot0/ i n3 p92/ t in2/ i n2 p91/ t in1/ i n1 p90/ t in0/ i n0 rx tx p65/ckot p64/p p g0 p63/p p g1 p62/sc k 2 p61/sot2 p60/sin2 p87/ i rq7 p86/ i rq6 p85/ i rq5 p84/ i rq4 p83/ i rq3 p82/ i rq2 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 50 10 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 76 hstx md 2 md 1 md 0 p8 1 / ir q1 p80/ irq0 p 57/ a n 7 p56/an 6/ s c k4 p55/an 5/ s o t4 p 54/ a n4/ s i n4 vs s p53/ an3 p52 / an 2/s c k3 p 51/ a n1/ s o t 3 p 50/ a n0/ s i n3 av ss av r l avr h av cc p 74/ da 01 p73/da00 dv ss dv rh p7 2 p7 1 p 21/ a 1 7 p 20/ a 1 6 p 17/ a d15 p 16/ a d14 p 15/ a d13 p 14/ a d12 p 13/ a d11 p 12/ a d10 p 11/ a d09 p 10/ a d08 p 07/ a d07 p 06/ a d06 p 05/ a d05 p 04/ a d04 p 03/ a d03 p 02/ a d02 p 01/ a d01 p 00/ a d00 vc c x1 x0 vs s x0 a x1 a pa 2 lqfp - 1 0 0 mb9058 0 series ( t o p view) fpt-100p-m05 1.4 pin assignment 6 chapter 1: overview MB90580 series 1.4.1 qfp-100 pin assignment figure 1.4b pin assignment of MB90580 (qfp-100) 80 79 78 77 76 75 x0a x1a pa2 rstx pa1 pa0 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rdx vss p32/wrlx p33/wrhx p34/hrq p35/hakx p36/rdy p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 vcc p45/sck1 p46/adtg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p97/pot p96/pwc p95/tot2/out1 p94tot1/out0 p93/tot0/in3 p92/tin2/in2 p91/tin1/in1 p90/tin0/in0 rx tx p65/ckot p64/ppg0 p63/ppg1 p62/sck2 p61/sot2 p60/sin2 p87irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 p82/irq2 hstx md2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dvss p73/da00 p74/da01 avcc avrh avrl avss p50/an0/sin3 p51/an1/sot3 p52/an2/sck3 p53/an3 vss p54/an4/sin4 p55/an5/sot4 p56/an6/sck4 p57/an7 p80/irq0 p81/irq1 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 vcc x1 x0 vss qfp - 100 MB90580 series ( top view) p47 c p71 p72 dvrh 26 27 28 29 30 md0 md1 fpt-100p-m06 1.5 pin functions MB90580 series chapter 1: overview 7 1.5 pin functions table 1.5a to table 1.5d lists the functions. table 1.5e to table 1.5g list the i/o circuit formats. table 1.5a pin functions (1/4) (stbc: with standby control) qfp lqfp pin name i/o circuit function 82 80 x0 a oscillator pin 83 81 x1 a oscillator pin 52 50 hstx c hardware standby input pin 77 75 rstx b reset input pin 85 to 92 83 to 90 p00 to p07 d (cmos/h) general-purpose i/o ports a pull-up resistor can be assigned (rd07-00='1') by using the pull-up resis- tor setting register (rdr0). (d07-00='1': invalid when set as output) ad00 to ad07 low-order data i/o or low-order address output (ad00 to 07) in external bus mode 93 to 100 91 to 98 p10 to p17 d (cmos/h) general-purpose i/o ports a pull-up resistor can be assigned (rd17-10='1') by using the pull-up resis- tor setting register (rdr1). (d17-10='1': invalid when set as output) ad08 to ad15 high-order data i/o or medium-order address output (ad08 to 15) in external 16-bit bus mode 1 to 8 99 to 6 p20 to p27 f (cmos/h) general-purpose i/o ports pins a16 to a19 when the corresponding bit of the hacr register is '0' in external bus mode a16 to a23 high-order address output (a16 to a19) when the corresponding bit of the hacr register is '1' in external bus mode 97 p30 f (cmos/h) general-purpose i/o port ale pin in external bus mode ale address fetch enable signal pin 10 8 p31 f (cmos/h) general-purpose i/o port rdx pin in external bus mode rdx read strobe output (rdx) pin 12 10 p32 f (cmos/h) general-purpose i/o port wrx pin when the wre bit is '1' in external bus mode wrlx low-order data write strobe output (wrlx) pin 13 11 p33 f (cmos/h) general-purpose i/o port wrhx pin when the wre bit of the epcr register is '1' in external 16-bit bus mode wrhx high-order data write strobe output (wrhx) pin 14 12 p34 f (cmos/h) general-purpose i/o port hrq pin when the hde bit of the epcr register is '1' in external bus mode hrq hold request input (hrq) pin 15 13 p35 f (cmos/h) general-purpose i/o port hakx pin when the hde bit of the epcr register is '1' in external bus mode hakx hold acknowledgment output (hakx) pin 16 14 p36 f (cmos/h) general-purpose i/o port rdy pin when the rye bit of the epcr register is '1' in external bus mode rdy external ready input (rdy) pin 17 15 p37 f (cmos/h) general-purpose i/o port clk pin when the cke bit of the epcr register is '1' in external bus mode clk machine cycle clock output (clk) pin 18 16 p40 e (cmos/h) general-purpose i/o port serial input (sin0) during uart0 operation open drain output port when od40 of the open drain control setting regis- ter (odr4) is set to '1' (d40='0': invalid when set as input) sino uart0 serial data input (sin0) pin 1.5 pin functions 8 chapter 1: overview MB90580 series table 1.5b pin functions (2/4) qfp lqfp pin name i/o circuit function 19 17 p41 e (cmos/h) general-purpose i/o port sot0 pin when the soe bit of the umc register is '1' open drain output port when od41 of the open drain control setting regis- ter (odr4) is set to '1' (d41='0': invalid when set as input) sot0 uart0 serial data output (sot0) pin 20 18 p42 e (cmos/h) general-purpose i/o port sot0 pin when the soe bit of the umc register is '1' open drain output port when od41 of the open drain control setting regis- ter (odr4) is set to '1' (d41='0': invalid when set as input) sck0 uart0 serial clock i/o (sck0) pin 21 19 p43 e (cmos/h) general-purpose i/o port serial input (sin1) during extended i/o serial operation open drain output port when od43 of the open drain control setting regis- ter (odr4) is set to '1' (d43='0': invalid when set as input) sin1 uart1 serial data input (sin1) pin 22 20 p44 e (cmos/h) general-purpose i/o port sot1 pin when the soe bit of the umc register is '1' open drain output port when od44 of the open drain control setting regis- ter (odr4) is set to '1' (d44='0': invalid when set as input) sot1 uart1 serial data output (sot1) pin 24 22 p45 e (cmos/h) general-purpose i/o port clock input (sck1) during extended i/o serial operation in external shift clock mode sck1 pin when the soe bit of the umc register is '1' open drain output port when od45 of the open drain control setting regis- ter (odr4) is set to '1' (d45='0': invalid when set as input) sck1 uart1 serial clock i/o (sck1) pin 25 23 p46 e (cmos/h) general-purpose i/o port open drain output port when od46 of the open drain control setting regis- ter (odr4) is set to '1' (d46='0': invalid when set as input) adtg a/d converter external trigger input pin 26 24 p47 e (cmos/h) general-purpose i/o port open drain output port when od47 of the open drain control setting register (odr4) is set to '1' (d47='0': invalid when set as input) 38 36 p50 g (cmos/h) general-purpose i/o port an0 analog input pin (an0) during a/d converter operation sin3 uart3 serial data input (sin3) pin 39 37 p51 g (cmos/h) general-purpose i/o port an1 analog input pin (an1) during a/d converter operation sot3 uart3 serial data output (sot3) pin 40 38 p52 g (cmos/h) general-purpose i/o port an2 analog input pin (an2) during a/d converter operation sck3 uart3 serial data output (sot3) pin 41 39 p53 g (cmos/h) general-purpose i/o port an3 analog input pins (an3) during a/d converter operation 43 41 p54 g (cmos/h) general-purpose i/o port an4 analog input pin (an4) during a/d converter operation sin4 uart4 serial data input (sin4) pin 44 42 p55 g (cmos/h) general-purpose i/o port an5 analog input pin (an5) during a/d converter operation sot4 uart4 serial data output (sot4) pin 1.5 pin functions MB90580 series chapter 1: overview 9 table 1.5c pin functions (3/4) qfp lqfp pin name i/o circuit function 45 43 p56 g (cmos/h) general-purpose i/o port an6 analog input pin (an6) during a/d converter operation sck4 uart4 serial data output (sot4) pin 46 44 p57 g (cmos/h) general-purpose i/o port an7 analog input pins (an7) during a/d converter operation 27 25 c 0.1uf capacitor connection pin for voltage supply stabilization. 28 26 p71 f (cmos/h) general-purpose i/o port sot3 pin when the soe bit of the umc register is '1' 29 27 p72 f (cmos/h) general-purpose i/o port clock input (sck3) during uart1 operation in external shift clock mode sck3 pin when the soe bit of the umc register is '1' 32 30 p73 h (cmos/h) general-purpose i/o port d/a output pin when the dae0 bit of the d/a control register (dacr) is '1' dao0 d/a output '0' pin during d/a converter operation 33 31 p74 f (cmos/h) general-purpose i/o port d/a output pin when the dae1 bit of the d/a control register (dacr) is '1' dao1 d/a output '1' pin during d/a converter operation 47 45 p80 f (cmos/h) general-purpose i/o port irq0 external interrupt request i/o 0 48 46 p81 f (cmos/h) general-purpose i/o port irq1 external interrupt request i/o 1 53 51 p82 f (cmos/h) general-purpose i/o port irq2 external interrupt request i/o 2 54 52 p83 f (cmos/h) general-purpose i/o port irq3 external interrupt request i/o 3 55 53 p84 f (cmos/h) general-purpose i/o port irq4 external interrupt request i/o 4 56 54 p85 f (cmos/h) general-purpose i/o port irq5 external interrupt request i/o 5 57 55 p86 f (cmos/h) general-purpose i/o port always enabled (stbc) irq6 external interrupt request i/o 6 58 56 p87 f (cmos/h) general-purpose i/o port always enabled (stbc) irq7 external interrupt request i/o 7 59 57 p60 d (cmos/h) general-purpose i/o port a pull-up resistor can be assigned (rd60='1') by using the pull-up resistor setting register (rdr6). (d60='1': invalid when set as output) sin2 uart2 serial data input (sin2) pin 60 58 p61 d (cmos/h) general-purpose i/o port sot1 pin when the soe bit of the umc register is '1' a pull-up resistor can be assigned (rd61='1') by using the pull-up resistor setting register (rdr6). (d61='1': invalid when set as output) sot2 uart2 serial data output (sout2) pin 61 59 p62 d (cmos/h) general-purpose i/o port clock input (sck2) during uart1 operation in external shift clock mode sck1 pin when the soe bit of the umc register is '1' a pull-up resistor can be assigned (rd62='1') by using the pull-up resistor setting register (rdr6). (d62='1': invalid when set as output) sck2 uart2 serial clock i/o (sck2) pin 1.5 pin functions 10 chapter 1: overview MB90580 series table 1.5d pin functions (4/4) qfp lqfp pin name i/o circuit function 62 60 p63 d (cmos/h) general-purpose i/o port a pull-up resistor can be assigned (rd63='1') by using the pull-up resistor setting register (rdr6). (d63='1': invalid when set as output) ppg00 ppg00 output when ppg is enabled 63 61 p64 d (cmos/h) general-purpose i/o port a pull-up resistor can be assigned (rd64='1') by using the pull-up resistor setting register (rdr6). (d64='1': invalid when set as output) ppg01 ppg01 output when ppg is enabled 64 62 p65 d (cmos/h) general-purpose i/o port a pull-up resistor can be assigned (rd65='1') by using the pull-up resistor setting register (rdr6). (d65='1': invalid when set as output) ckot ckot output during ckot operation 65 63 tx i iebus output when iebus is enabled 66 64 rx j iebus input when iebus is enabled 67 to 69 65 to 67 p90 to p92 f (cmos/h) general-purpose i/o port tin0 to tin2 event input pins for reload timers 0,1 and 2. as these inputs are used con- tinuously during reload timer input operation, outputs to these pins from other functions must be avoided unless performed intentionally. in0 to in2 input capture channels 0 - 2 trigger inputs 70 68 p93 f (cmos/h) general-purpose i/o port tot0 output pins for reload timer 0. this function applies when the output for reload timers 0 is enabled. in3 input capture channel 3 trigger input 71 to 72 69 to 70 p94 to p95 f (cmos/h) general-purpose i/o port tot1, tot2 output pins for reload timers 1 and 2. this function applies when the out- puts for reload timers 1 and 2 are enabled. out0, out1 output comparison channels 0 - 1 event outputs 73 71 p96 f (cmos/h) general-purpose i/o port pwc pwc input 74 72 p97 f (cmos/h) general-purpose i/o port 75, 76 73, 74 pa0, pa1 f (cmos/h) general-purpose i/o port 78 76 pa2 f (cmos/h) general-purpose i/o port 79 77 x1a a oscillator input 80 78 x0a a oscillator input 34 32 av cc a/d converter power supply pin 37 35 av ss a/d converter power supply pin 35 33 avrh a/d converter external reference power supply pin 36 34 avrl a/d converter external reference power supply pin 30 28 dvrh d/a converter external reference power supply pin 31 29 dvss d/a converter power supply pin 49 to 51 47 to 49 md0 to md2 c operation mode specification input pin connect directly to vcc or vss. 23, 84 21, 82 v cc power supply (5 v) input pin 11, 42, 81 9, 40, 79 vss power supply (0 v) input pin 1.5 pin functions MB90580 series chapter 1: overview 11 table 1.5e i/o circuit format (1) class circuit remarks a oscillation feedback resistor: 1 m w approx. b hysteresis input with pull-up resistor: 50 k w approx. c hysteresis input port d with input pull-up resistor control cmos level output hysteresis input with standby control resistor: 50 k w approx. x1 x0 standby control signal hys hys ctl hys standby control signal 1.5 pin functions 12 chapter 1: overview MB90580 series table 1.5f i/o circuit format (2) class circuit remarks e cmos level output with open drain control hysteresis input with standby contro f cmos level output hysteresis input with standby control g cmos level output hysteresis input with standby control analog input open drain control signal hys standby control signal hys standby control signal analog input hys standby control signal 1.5 pin functions MB90580 series chapter 1: overview 13 table 1.5g i/o circuit format (3) class circuit remarks h cmos level output hysteresis input with standby control analog output shared with da output i cmos level output j hysteresis input hys standby control signal da output 1.6 handling the device 14 chapter 1: overview MB90580 series 1.6 handling the device (1) preventing latch-up cmos ic chips may suffer latch-up under the following conditions: a voltage higher than vcc or lower than vss is applied to an input or output pin. a voltage higher than the rated voltage is applied between vcc and vss. the avcc power supply is applied before the vcc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. (2) handling unused input pins do not leave unused input pins open, as doing so may cause misoperation of the device. use a pull-up or pull-down resistor. (3) using external clock to use external clock, drive the x0 and x1 pins in reverse phase. figure 1.6a is a diagram of how to use external clock.. figure 1.6a using external clock (4) power supply pins (vcc/vss) ensure that all vcc-level power supply pins are at the same potential. in addition, ensure the same for all vss-level power supply pins. (see the figure below.) if there are more than one vcc or vss system, the device may operate incorrectly even within the guaranteed operating range. figure 1.6b connection of power pins x0 x1 MB90580 series vcc vss vss vcc vss vcc MB90580 series vcc vss vcc vss chapter 2: cpu 2.1 cpu the f 2 mc-16lx cpu core is a 16-bit cpu designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted electronic appliances. the f 2 mc-16lx instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. in addition to 16-bit data, the f 2 mc-16lx cpu core can process 32-bit data by using an internal 32-bit accumulator. (32-bit data can be processed with some instructions.) up to 16 mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. the instruction system, based on the f 2 mc-8 a-t architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and divi- sion instructions, and enhancing bit processing. the features of the f 2 mc-16lx cpu are explained below. ? minimum instruction execution time: 62.5 ns (at 4-mhz oscillation, 4 times multiplication) ? maximum memory space: 16 mbytes, accessed in linear or bank mode ? instruction set optimized for controller applications rich data types: bit, byte, word, long word extended addressing modes: 23 types high-precision operation (32-bit length) based on 32-bit accumulator signed multiply and division, enhanced reti instruction ? powerful interrupt functions eight priority levels (programmable) ? cpu-independent automatic transfer up to 16 channels of extended intelligent i/o service ? instruction set compatible with high-level language (c)/multitasking system stack pointer/instruction set symmetry/barrel-shift instructions ? improved execution speed: 4-byte queue 2.1 cpu 16 chapter 2: cpu MB90580 series 2.1.1 memory space n outline of cpu memory space an f 2 mc-16lx cpu has a 16-mbyte memory space. all data program input and output managed by the f 2 mc-16lx cpu are located in this 16-mbyte memory space. the cpu accesses the resources by indicating their addresses using a 24-bit address bus. (see figure 2.1.1a.). figure 2.1.1a sample relationship between f 2 mc-16lx system and memory map f 2 mc-16lx cpu [device] program data interrupt peripheral general- program area data area interrupt controller peripheral circuits general-purpose ports circuits purpose ports ffffff h ff8000 h 810000 h 800000 h 0000c0 h 0000b0 h 000020 h 000000 h 2.1 cpu MB90580 series chapter 2: cpu 17 n address generation types the f 2 mc-16lx cpu has two address generation methods. one is the linear method in which an entire 24-bit address is specified by an instruction. the other method is the bank method in which the high-order eight bits of an address is specified by an appropriate bank register while the low-order 16 bits of the same address is specified by an instruction. there are two types of linear method. one specifies a 24-bit address directly by using operands. the other method cites the low-order 24 bits of a 32-bit general-purpose register value as an address. (see figure 2.1.1b.) figure 2.1.1b sample linear addressing n bank addressing types in the bank method, the 16-mbyte space is divided into 256 64-kbyte banks. the following five bank registers are used to specify the banks corresponding to each space: ? program bank register (pcb) ? data bank register (dtb) ? user stack bank register (usb) ? system stack bank register (ssb) ? additional bank register (adb) 17 12 452d 3456 17452d h 123456 h jmpp 123456 h example 1 linear method (24-bit operand specification) old program counter new program counter next instruction + program bank + program bank xxxx +7 rl1 3a example 2 linear method (32-bit register indirect specification) old al new al (the high-order eight bits are ignored.) jmpp 123456h mov a, @ rl1+7 240906f9 090700 h 003a 2.1 cpu 18 chapter 2: cpu MB90580 series the 64-kbyte bank specified by the pcb is called a program (pc) space. the pc space contains instruction codes, vector tables, and immediate value data, for example. the 64-kbyte bank specified by the dtb is called a data (dt) space. the dt space contains readable/ writable data, and control/data registers for internal and external resources. the 64-kbyte bank specified by the usp or ssp is called a stack (sp) space. the sp space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. the s flag in the condition code register determines the stack space to be accessed. the 64-kbyte bank specified by the adb is called an additional (ad) space. the ad space, for example, contains data that cannot fit into the dt space. table 2.1.1a lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. to use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. this enables access to the bank space corresponding to the specified prefix code. after reset, the dtb, usb, ssb, and adb are initialized to 00h. the pcb is initialized to a value spec- ified by the reset vector. after reset, the dt, sp, and ad spaces are allocated in bank 00h (000000h to 00ffffh), and the pc space is allocated in the bank specified by the reset vector. figure 2.1.1c is an example of a memory space divided into register banks. figure 2.1.1c physical addresses of each space table 2.1.1a default space default space addressing mode program space pc indirect, program access, branch data space addressing mode using @rw0, @rw1, @rw4, or @rw5, @a, addr16, and dir stack space addressing mode using pushw, popw, @rw3, or @rw7 additional space addressing mode using @rw2 or @rw6 ff h b3 h 92 h 68 h 4b h ffffff h ff0000 h b3ffff h 920000 h 68ffff h 680000 h 4bffff h 4b0000 h 000000 h physical address program space additional space user stack space data space system stack space : pcb (program bank register) : adb (additional bank register) : usb (user stack bank register) : dtb (data bank register) : ssb (system stack bank register) 92ffff h b30000 h 2.1 cpu MB90580 series chapter 2: cpu 19 n multi-byte data allocation in memory space figure 2.1.1d is a diagram of multi-byte data configuration in memory. the low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. figure 2.1.1d sample allocation of multi-byte data in memory data is written to memory from the low-order addresses. therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. if a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written. n accessing multi-byte data fundamentally, accesses are made within a bank. for an instruction accessing a multi-byte data item, address ffffh is followed by address 0000h of the same bank. figure 2.1.1e is an example of an instruction accessing multi-byte data. figure 2.1.1e execution of movw a, 080ffffh h l 01010101 11001100 11111111 00010100 msb lsb 01010101 11001100 11111111 00010100 address n l h 80ffff h 800000 h 01 h 23 h ?? ?? 23 h 01 h al before execution al after execution 2.1 cpu 20 chapter 2: cpu MB90580 series 2.1.2 registers the f 2 mc-16lx registers are largely classified into two types: special registers in the cpu and general-purpose registers in memory. the special registers are dedicated internal hardware of the cpu, and their applications are limited by the cpu architecture. the general-purpose registers share the cpu address space with ram. the general-purpose registers are the same as the special registers in that they can be accessed without using an address. the applications of the general-purpose registers can be specified by the user however, as is ordinary memory space. n special registers the f 2 mc-16lx has the following 13 special registers: ? accumulator (a=ah:al): two 16-bit accumulators (can be used as a single 32-bit accumulator.) ? user stack pointer (usp): 16-bit pointer indicating the user stack area ? system stack pointer (ssp): 16-bit pointer indicating the system stack area ? processor status (ps): 16-bit register indicating the system status ? program counter: 16-bit register holding the address of the program ? program bank register: 8-bit register indicating the pc space ? data bank register: 8-bit register indicating the dt space ? user stack bank register (usb): 8-bit register indicating the user stack space ? system stack bank register (ssb): 8-bit register indicating the system stack space ? additional bank register (adb): 8-bit register indicating the ad space ? direct page register (dpr): 8-bit register indicating a direct page figure 2.1.2a special registers accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register ah al usp ssp ps pc drp pcb dtb usb ssb adb 8 bit 16 bit 32 bit 2.1 cpu MB90580 series chapter 2: cpu 21 n general-purpose registers the f 2 mc-16lx general-purpose registers are located from addresses 000180h to 00037fh (maximum configuration) of main storage. the register bank pointer (rp) indicates which of the above addresses are currently being used as a register bank. each bank has the following three types of registers. these registers are mutually dependent as described in figure 2.1.2b. ? r0 to r7: 8-bit general-purpose register ? rw0 to rw7: 16-bit general-purpose register ? rl0 to rl3: 32-bit general-purpose register figure 2.1.2b general-purpose registers the relationship between the high-order and low-order bytes of a byte or word register is expressed as follows: rw (i+4) = r (i*2+1) *256+r (i*2) [i=0 to 3] the relationship between the high-order and low-order bytes of rli and rw can be expressed as follows: rl (i) = rw (i*2+1) *65536+rw (i*2) [i=0 to 3] n program counter (pc) the pc register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the cpu. the high-order eight bits of the address are indicated by the pcb. the pc register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. the pc register can also be used as a base pointer for operand access. figure 2.1.2c program counter 000180 h + rp*10 h msb lsb rw0 rw1 rw2 rw3 r1 r0 r3 r5 r7 r2 r4 r6 rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 16 bit first address of low-order high-order general-purpose register pcb pc fe h a bcd h feabcd h next instruction to be executed 2.1 cpu 22 chapter 2: cpu MB90580 series n accumulator (a) the a register consists of two 16-bit arithmetic operation registers (ah and al). the a register is used as a temporary storage for operation results and transfer data. during 32-bit data processing, ah and al are used together. only al is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see figures 2.1.9 and 2.1.10). the data stored in the a register can be operated upon with the data in memory or registers (ri, rwi, or rli). in the same manner as with the f 2 mc-8l, when a word or shorter data item is transferred to al, the previous data item in al is automati- cally sent to ah (data preservation function). the data preservation function and operation between al and ah help improve processing efficiency. when a byte or shorter data item is transferred to al, the data is sign-extended or zero-extended and stored as a 16-bit data item in al. the data in al can be handled either as word or byte long. when a byte-processing arithmetic operation instruction is executed on al, the high-order eight bits of al before operation are ignored. the high-order eight bits of the operation result all become zeroes. the a register is not initialized by a reset. the a register holds an undefined value immediately after a reset. figure 2.1.2d 32-bit data transfer figure 2.1.2e al-ah transfer xxxx h xxxx h 8f74 h 2b52 h dtb a6 h +6 rw1 a61540 h a6153e h msb lsb 8f h 2b h 15 h 74 h 52 h 38 h ah al movl a,@rw1+6 old a new a +6 rw1 a61540 h a6153e h xxxx h 1234 h 1234 h 2b52 h dtb a6 h 8f h 2b h 15 h 74 h 52 h 38 h msb lsb movw a,@rw1+6 old a new a 2.1 cpu MB90580 series chapter 2: cpu 23 n user stack pointer (usp) and system stack pointer (ssp) usp and ssp are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. the usp and ssp registers are used by stack instructions. the usp register is enabled when the s flag in the processor status register is '0,' and the ssp register is enabled when the s flag is '1' (see figure 2.1.2f). since the s flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by ssp during interrupt processing. ssp is used for stack processing in an interrupt routine, while usp is used for stack process- ing outside an interrupt routine. if the stack space is not divided, use only the ssp. during stack processing, the high-order eight bits of an address are indicated by ssb (for ssp) or usb (for usp). usp and ssp are not initialized by a reset. instead, they hold undefined values. figure 2.1.2f stack manipulation instruction and stack pointer note: specify an even-numbered address in the stack pointer whenever possible. al a624 h usb usp ssp ssb 0 c6 h 56 h f328 h 1234 h c6f326 h msb lsb xx xx al a624 h usb usp ssp ssb 0 c6 h 56 h f326 h 1234 h c6f326 h 24 h a6 h al a624 h usb usp ssp ssb c6 h 56 h f328 h 1234 h 561232 h xx xx 1 al a624 h usb usp ssp ssb 1 c6 h 56 h f328 h 1232 h 561232 h 24 h a6 h example 1 pushw a when the s flag is '0' before execution s flag after execution user stack is used because example 2 pushw a when the s flag is '1' system stack is used because the s flag is '1.' the s flag is '0.' 2.1 cpu 24 chapter 2: cpu MB90580 series n processor status (ps) the ps register consists of the bits controlling the cpu operation and the bits indicating the cpu status. as shown in figure 2.1.2g, the high-order byte of the ps register consists of a register bank pointer (rp) and an interrupt level mask register (ilm). the rp indicates the start address of a register bank. the low-order byte of the ps register is a condition code register (ccr), containing the flags to be set or reset depending on the results of instruction execution or interruptoccurrences. figure 2.1.2g ps structure (1)condition code register (ccr) figure 2.1.2h condition code register configuration i:interrupt enable flag: interrupts other than software interrupts are enabled when the i flag is 1 and are masked when the i flag is 0. the i flag is cleared by a reset. s:stack flag: when the s flag is 0, usp is enabled as the stack manipulation pointer. when the s flag is 1, ssp is enabled as the stack manipulation pointer. the s flag is set by an interrupt reception or a reset. t:sticky bit flag: 1 is set in the t flag when there is at least one '1' in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. otherwise, 0 is set in the t flag. in addition, '0' is set in the t flag when the shift amount is zero. n:negative flag: the n flag is set when the msb of the operation result is '1,' and is otherwise cleared. z:zero flag: the z flag is set when the operation result is all zeroes, and is otherwise cleared. v:overflow flag: the v flag is set when an overflow of a signed value occurs as a result of operation execution and is otherwise cleared. c:carry flag: the c flag is set when a carry-up or carry-down from the msb occurs as a result of operation execution and is otherwise cleared. ilm rp ccr ps 15 13 12 8 7 0 76 54 3 210 - istnzvc : ccr - 01***** initial value *: undefined 2.1 cpu MB90580 series chapter 2: cpu 25 (2) register bank pointer (rp) the rp register indicates the relationship between the general-purpose registers of the f2mc-16lx and the internal ram addresses. specifically, the rp register indicates the first memory address of the currently used register bank in the following conversion expression: [00180h + (rp)*10h] (see figure 2.1.2i). the rp register consists of five bits, and can take a value between 00h and 1fh. register banks can be allocated at addresses from 000180h to 000370h in memory. even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal ram. the rp register is initialized to all zeroes by a reset. an instruc- tion may transfer an eight-bit immediate value to the rp register; however, only the low-order five bits of that data are used. figure 2.1.2i register bank pointer (3) interrupt level mask register (ilm) the ilm register consists of three bits, indicating the cpu interrupt masking level. an interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see table 2.1.2a). therefore, for an interrupt to be accepted, its level value must be smaller than the current ilm value. when an interrupt is accepted, the level value of that interrupt is set in ilm. thus, an interrupt of the same or lower level cannot be accepted subsequently. ilm is initialized to all zeroes by a reset. an instruction may transfer an eight-bit immediate value to the ilm register, but only the low-order three bits of that data are used. figure 2.1.2j interrupt level register table 2.1.2a levels indicated by the interrupt level mask (ilm) register ilm2 ilm1 ilm0 level value acceptable interrupt level 0000 interrupt disabled 0011 0 only 0102level value smaller than 1 0113level value smaller than 2 1004level value smaller than 3 1015level value smaller than 4 1106level value smaller than 5 1117level value smaller than 6 initial value b3 b2 b1 b0 b4 0 0 000 : rp initial value ilm2 ilm1 ilm0 000 : ilm 2.1 cpu 26 chapter 2: cpu MB90580 series n register bank a register bank consists of eight words. the register bank can be used as the following general-purpose registers for arithmetic operations: byte registers r0 to r7, word registers rw0 to rw7, and long word registers rl0 to rl3. in addition, the register bank can be used as instruction pointers. table 2.1.2b lists the functions of the registers. table 2.1.2c indicates the relationship between the registers. in the same manner as for an ordinary ram area, the register bank values are not initialized by a reset. the status before a reset is maintained. when the power is turned on, however, the register bank will have an undefined value. table 2.1.2b register functions r0 to r7 used as operands of instructions. note: r0 is also used as a counter for barrel shift or normalization instructions. rw0 to rw7 used as pointers. used as operands of instructions. note: rw0 is used as a counter for string instructions. rl0 to rl3 used as long pointers. used as operands of instructions. table 2.1.2c relationship between registers rw0 rl0 rw1 rw2 rl1 rw3 r0 rw4 rl2 r1 r2 rw5 r3 r4 rw6 rl3 r5 r6 rw7 r7 2.1 cpu MB90580 series chapter 2: cpu 27 n program counter bank register (pcb) 2.1 cpu 28 chapter 2: cpu MB90580 series 2.1.3 prefix codes placing a prefix code before an instruction partially changes the operation of the instruction. three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. n bank select prefix the memory space used for accessing data is determined for each addressing mode. when a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. use the following instructions with care: (1) string instructions (movs, movsw, sceq, scweq, fils, filsw) the bank register specified by an operand is used regardless of the prefix. (2)stack manipulation instructions (pushw, popw) ssb or usb is used according to the s flag regardless of the prefix. (3)i/o access instructions the io space of the bank is used regardless of the prefix. (4)flag change instructions (and ccr,#imm8, or ccr,#imm8) the instruction is executed normally, but the prefix affects the next instruction. (5)popw ps ssb or usb is used according to the s flag regardless of the prefix. the prefix affects the next instruction. (6)mov ilm,#imm8 the instruction is executed normally, but the prefix affects the next instruction. (7)reti ssb is used regardless of the prefix. table 2.1.3a bank select prefix bank select prefix space selected pcb pc space dtb data space adb ad space spb either the ssp or usp space is used according to the stack flag value. mov a, io / mov io, a /movx a, io / movw a, io /movw io, a / mov io, #imm8 movw io, #imm16 / movb a, io:bp / movb io:bp, a /setb io:bp / clrb io:bp bbc io:bp, rel / bbs io:bp, rel wbtc, wbts 2.1 cpu MB90580 series chapter 2: cpu 29 n common register bank prefix (cmr) to simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the rp value. when cmr is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when rp=0) at addresses from 000180h to 00018fh regardless of the current rp value. use the following instructions with care: (1)string instructions (movs, movsw, sceq, scweq, fils, filsw) if an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. thus, the string instruction is executed falsely after the interrupt is processed. do not prefix any of the above string instructions with cmr. (2)flag change instructions (and ccr,#imm8, or ccr,#imm8, popw ps) the instruction is executed normally, but the prefix affects the next instruction. (3)mov ilm,#imm8 the instruction is executed normally, but the prefix affects the next instruction. n flag change disable prefix to disable flag changes, use the flag change disable prefix code (ncc). placing ncc before an instruction disables flag changes associated with that instruction. use the following instructions with care: (1) string instructions (movs, movsw, sceq, scweq, fils, filsw) if an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code becomes invalid when the string instruction is resumed after the interrupt is processed. thus, the string instruction is executed incorrectly after the interrupt is processed. do not prefix any of the above string instructions with ncc. (2) flag change instructions (and ccr,#imm8, or ccr,#imm8, popw ps) the instruction is executed normally, but the prefix affects the next instruction. (3)interrupt instructions (int #vct8, int9, int addr16, intp addr24, reti) ccr changes according to the instruction specifications regardless of the prefix. (4)jctx @a ccr changes according to the instruction specifications regardless of the prefix. (5)mov ilm,#imm8 the instruction is executed normally, but the prefix affects the next instruction. n interrupt disable instructions interrupt requests are not sampled for the following ten instructions: if a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. for details, see figure 2.1.3a. figure 2.1.3a interrupt disable instruction mov ilm,#imm8 pcb spb or ccr,#imm8 ncc and ccr,#imm8 adb cmr popw ps dtb interrupt disable instruction interrupt request interrupt acceptance (a) ordinary instruction (a) 2.1 cpu 30 chapter 2: cpu MB90580 series n restrictions on interrupt disable instructions and prefix instructions when a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. figure 2.1.3b interrupt disable instructions and prefix codes n consecutive prefix codes when competitive prefix codes are placed consecutively, the latter becomes valid. figure 2.1.3c consecutive prefix codes in the figure above, competitive prefix codes are pcb, adb, dtb, and spb. mov a, ff h ccr:xxx10xx ncc mov ilm,#imm8 add a,01 h ccr:xxx10xx interrupt disable instruction ccr does not change with ncc. adb dtb pcb add a,01 h prefix code pcb is valid as the prefix code chapter 3: memory 3.1 memory access modes in the f 2 mc-16lx, there are several modes for access methods, access areas, and test methods. in this module, the following classifications apply: n operation mode operation mode means the mode for controlling the device operation status. the operation mode is specified by the mdx mode setting pin and the ex bit in mode data. by selecting an operation mode, normal operation, internal test program activation, or special test function activation can be performed. n bus mode bus mode means the mode for controlling the internal rom operation and external access function. the bus mode is specified by the mdx mode setting pin and the mx bit in mode data. the mdx mode setting pin specifies the bus mode for reading the reset vector and mode data, and the mx bit in mode data specifies the bus mode for normal operation. n access mode access mode means the mode for controlling the external data bus width. the access mode is specified by the mdx mode setting pin and the sx bit in mode data. by selecting an access mode, an 8- or 16-bit external data bus is specified. table 3.1a memory access mode operation mode bus mode access mode (external data bus width) run single chip internal rom, external bus 8 bit 16 bit external rom, external bus 8 bit 16 bit eprom write test functions 3.1 memory access modes 32 chapter 3: memory MB90580 series 3.1.1 mode pins table 3.1.1a describes the operations specified by combinations of the md2 to md0 external pins. note: when using internal vector mode 0, the initial value of iobs and lmbs are 0. if iobs and lmbs are set afterwards, the address range 0000c0h..0000ffh and 002000h..7fffffh will use 16-bit data bus. table 3.1.1a mode pins and modes mode pin setting md2 md1 md0 mode name reset vector access area external data bus width remarks 0 0 0 external vector mode 0 external 8 bits 0 0 1 external vector mode 1 external 16 bits reset vector, 16-bit bus width access 0 1 0 (specification inhibited) 0 1 1 internal vector mode internal (mode data) reset sequence are based on mode data. 1 0 0 (specification inhibited) 1 0 1 1 1 0 1 1 1 eprom write 3.1 memory access modes MB90580 series chapter 3: memory 33 3.1.2 mode data mode data is stored at ffffdf h of main memory and used for controlling the cpu operation. this data is fetched during a reset sequence and stored in the mode register inside the device. the mode register value can be changed only by a reset sequence. the setting of this register is valid after the reset sequence. always set the reserved bits to '0.' here is a diagram of the setting of the bits. [bit 7, 6] : bus mode setting bits these bits are used to specify the operation mode after the reset sequence is completed. here shows the relationship between the bits and the functions. [bit 3] : mode setting bits these bits are used to specify the bus mode or access mode after the reset sequence is completed. the following table shows the relationship between the bits and the functions. m1 m0 function remarks 0 0 single chip mode 0 1 internal rom and external bus mode 1 0 external rom and external bus mode 1 1 (inhibited) s0 function remarks 0 external data bus, 8-bit mode 1 external data bus, 16-bit mode s0 m1 m0 6543210 7 mode data bit no. address: ffffdf h 3.1 memory access modes 34 chapter 3: memory MB90580 series 3.1.3 bus mode figure 3.1.3a shows correspondence between the access areas and physical addresses for each bus mode. figure 3.1.3a access areas and physical addresses in each bus mode ffffff h fe0000 h 010000 h 004000 h 002000 h 000100 h 0000c0 h rom rom ram ram rom ram i/o i/o i/o address #1 address #2 address #3 000000 h : no access : internal access : external access single chip internal rom, external bus external rom, external bus . device address #1 address #2 address #3 mb90583 fe0000h 004000h 001900h mb90f583 fe0000h 004000h 001900h mb90v580 (fe0000h) 004000h 001900h (ff bank image) rom (ff bank image) (with rom mirror function) (with rom mirror function) note: if rom mirroring function is not wanted, please refer to chapter 22, rom mirroring module. note: the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced with- out using the far specification in the pointer declaration.for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. note: the rom area in bank ff exceeds 48 kbytes, and its entire image cannot be shown in bank 00. note: with the mb90f583 and mb90583, the image between ff4000h and ffffff h is visible in bank 00, while the image between fe0000 h and ff3fff h is visible only in bank fe or ff 3.1 memory access modes MB90580 series chapter 3: memory 35 n recommended setting table 3.1.3a lists a sample recommended setting of mode pins and mode data. note: i/o signals appearing on an external pin connected to this module vary with the mode. table 3.1.3b lists the external pin function in each modes note: the high-order bits of an address and wrx, wrlx, wrhx, hakx, hrq, rdy, and clk can be used as ports depending on function selection. table 3.1.3a sample recommended setting of mode pins and mode data sample setting md2 md1 md0 m1 m0 s0 single chip 0 1 1 0 0 internal rom and external bus mode, 16-bit bus 0 1 1 0 1 1 internal rom and external bus mode, 8-bit bus 0 1 1 0 1 0 external rom and external bus mode, 16-bit bus, vector 16 bus width 0 0 1 1 0 1 external rom and external bus mode, 8-bit bus 0 0 0 1 0 0 table 3.1.3b modes and related external pin operations pin name function single chip external bus extension eprom write 8 bits 16 bits p07 to p00 port ad07 to 00 d07 to 00 p17 to p10 a15 to 08 ad15 to 08 a15 to 08 p27 to p20 a23 to 16 a07 to 00 p30 ale a16 p31 rdx cex p32 wrx wrlx oex p33 port wrhx pgmx p34 hrq unused p35 hakx p36 rdy p37 clk 3.2 external memory access 36 chapter 3: memory MB90580 series 3.2 external memory access to access external memory and peripherals, the f 2 mc-16lx supplies the following address, data, and control signals: clk (p37) : machine cycle clock (kbp) rdy (p36) : external ready input pin wrhx (p33) : write signal for high-order 8 bits of data bus wrlx (p32) : write signal for low-order 8 bits of data bus rdx (p31) : read signal ale (p30) : address latch enable signal the external bus pin control circuit controls the external bus pins for externally extending the cpu address/data bus. 3.2.1 block diagram figure 3.2.1a external bus pin control circuit p0 p3 p2 p1 p0 p3 rb p0 data p0 direction data control address access access control control control 3.2 external memory access MB90580 series chapter 3: memory 37 3.2.2 registers and register details lmr1 lmr0 hmr0 15 14 13 12 11 10 9 8 hmr1 ior1 automatic ready function selection register address: 0000a5 h read/write initial value bit no. (w) (0) (-) (w) (1) arsr ior0 (-) (-) (-) (w) (0) (w) (0) (w) (1) (w) (0) e19 e18 e17 e16 e20 e21 e23 external address output control register address: 0000a6 h read/write initial value bit no. (w) (0) hacr e22 (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) 6543210 7 hmbs wre lmbs iobs 15 14 13 12 11 10 9 8 hde cke bus control signal selection register address: 0000a7 h read/write initial value bit no. (w) (0) (w) (0) ecsr rye (-) (-) (w) (0) (w) (0) (w) (0) (w) (0) (w) (1/0) 3.2 external memory access 38 chapter 3: memory MB90580 series 3.2.2.1 automatic ready function selection register [bits 15 and 14]: ior1 and ior0 these bits specify the automatic wait function for external access to the area between 000000 h and 0000ff h . the initial value is '00b.' [bits 13 and 12]: hmr1 and hmr0 these bits specify the automatic wait function for external access to the area between 800000 h and ffffff h . the initial value is '11b.' [bits 9 and 8]: lmr1 and lmr0 these bits specify the automatic wait function for external access to the area between 002000 h and 7fffff h . the initial value is '00b.' ior1 ior0 setting 0 0 automatic wait disabled 0 1 one machine cycle of automatic wait for external access 1 0 two machine cycles of automatic wait for external access 1 1 three machine cycles of automatic wait for external access hmr1 hmr0 setting 0 0 automatic wait disabled 0 1 one machine cycle of automatic wait for external access 1 0 two machine cycles of automatic wait for external access 1 1 three machine cycles of automatic wait for external access lmr1 lmr0 setting 0 0 automatic wait disabled 0 1 one machine cycle of automatic wait for external access 1 0 two machine cycles of automatic wait for external access 1 1 three machine cycles of automatic wait for external access -- lmr1 lmr0 hmr0 15 14 13 12 11 10 9 8 hmr1 ior1 address: 0000a5 h read/write initial value bit no. (w) (0) (-) (w) (1) arsr ior0 (-) (-) (-) (w) (0) (w) (0) (w) (1) (w) (0) 3.2 external memory access MB90580 series chapter 3: memory 39 3.2.2.2 external address output control register this register controls the external output of addresses (a19 to a16). the bits corresponds to addresses a19 to a16, controlling the address output pins as described below. this register cannot be accessed when the device is in single chip mode. in that case, all pins are used as i/o ports regardless of the value of this register. all bits of this register are write-only bits. '1' is always read from these bits. these bits are initialized to '0' upon a reset. table 3.2.0a selecting the high-order address bit output control 0 the corresponding pin is used as an address output (axx). 1 the corresponding pin is used as an i/o port (pxx). e19 e18 e17 e16 e20 e21 e23 address: 0000a6 h read/write initial value bit no. (w) (0) hacr e22 (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) 6543210 7 3.2 external memory access 40 chapter 3: memory MB90580 series 3.2.2.3 bus control signal selection register this register is used to set the bus control function in external bus mode. this register cannot be accessed when the device is in single chip mode. in that case, all pins are used as i/o ports regardless of the value of this register. all bits of this register are write-only bits. '1' is always read from these bits. [bit 15]: cke this bit controls the external clock (clk) output as described below. this bit is initialized to '0' upon a reset. [bit 14]: rye this bit controls the external ready (rdy) input as described below. this bit is initialized to '0' upon a reset. [bit 13]: hde this bit specifies whether to enable i/o of hold-related pins. this bit controls the hold request input (hrq) and hold acknowledge output (hakx) pins as described below. this bit is initialized to '0' upon a reset. [bit 12]: iobs this bit specifies the bus size when an area between 0000c0h and 0000ffh is externally accessed in 16-bit external data bus mode. the size is controlled as described below. this bit is initialized to '0' upon a reset. 0 i/o port (p37) operation (clock output disabled) 1 clock signal (clk) output enabled 0 i/o port (p36) operation (external rdy input disabled) [default] 1 external ready (rdy) input enabled 0 i/o port (p35 and p34) operation (hold function i/o disabled) [default] 1 hold request (hrq) input/hold acknowledge (hakx) output enabled 0 16-bit bus size access [default] 1 8-bit bus size access hmbs wre lmbs iobs 15 14 13 12 11 10 9 8 hde cke bus control signal selection register address: 0000a7 h read/write initial value bit no. (w) (0) (w) (0) ecsr rye (-) (-) (w) (0) (w) (0) (w) (0) (w) (0) (w) (0) 3.2 external memory access MB90580 series chapter 3: memory 41 [bit 11]: hmbs this bit specifies the bus size when an area between 800000 h and ffffff h is externally accessed in 16-bit external data bus mode. the size is controlled as described below. this bit is initialized to '1' upon a reset in external vector mode 2. in any other mode, this bit is initialized to '0' upon a reset. [bit 10]: wre this bit controls the output of the external write signal pin (wrhx and wrlx pins in 16-bit bus mode and wrx pin in 8-bit bus mode) as described below. in 8-bit external data bus mode, p33 is used as an i/o port regardless of the value of this register. this bit is initialized to '0' upon a reset. [bit 9]: lmbs this bit specifies the bus size when an area between 002000 h and 7fffff h is externally accessed in 16-bit external data bus mode. the size is controlled as described below. this bit is initialized to '1' upon a reset. note: in 16-bit bus mode, set p33 and p32 in input mode (set '0' in bits 3 and 2 of ddr3) when enabling the wrhx and wrlx functions by the wre bit. in 8-bit bus mode, set p32 in input mode (set '0' in bit 2 of ddr3) when enabling the wrx function by the wre bit. even if rdy or hrq input is enabled by the rye or hde bit, the i/o port function of the port is valid. therefore, ensure that '0' (input mode) is written to the ddr3 bit corresponding to the port. 0 16-bit bus size access [default in mode other than external vector mode 2] 1 8-bit bus size access [default in external vector mode 2] 0 i/o port (p33 and p32) operation (write signal output disabled) [default] 1 write strobe signal (wrhx/wrlx or wrx) output enabled 0 16-bit bus size access [default] 1 8-bit bus size access 3.2 external memory access 42 chapter 3: memory MB90580 series 3.2.1 operations MB90580 has a variety of access method and access area modes. see section 3.1 ,memory access modes (1) external memory access control signals external memory is accessed in three cycles while the ready function is not used. figure 3.2.4 shows the concept of external access timing. the 8-bit bus width access in external 16-bit bus mode is used to read or write to an 8-bit peripheral chip when both 8- and 16-bit peripheral chips are connected to the external bus. sine the 8-bit bus width access is executed using the low-order 8 bits of the data bus, ensure that the 8-bit peripheral chips are connected to the low-order 8 bits of the data bus. use the hmbs, lmbs, and iobs bits of epcr to specify whether to perform 16- or 8-bit bus width access in external 16-bit bus mode. if only an address and ale assert signal are output and rdx, wrx, wrlx, and wrhx are not asserted, the bus operation may not be actually performed. ensure that a peripheral chip is not accessed by only an ale signal. n external 8-bit bus mode figure 3.2.1a external memory access timing chart p37/clk p33 p32/wrx p31/rdx p30/ale p27 to 20/a23 to 16 p17 to 10/a15 to 08 p07 to 00/ad07 to 00 read write (port data) read address write address read data write data read read address read write address address write address read address read address read address 3.2 external memory access MB90580 series chapter 3: memory 43 n external 16-bit bus mode figure 3.2.1b external memory access timing chart p37/clk p33/wrhx p32/wrlx p31/rdx p30/ale p27 to 20/a23 to 16 p17 to 10/ad15 to 08 p07 to 00/ad07 to 00 odd-number address odd-number address byte read byte write read address invalid write address read data undefined write data read address read address write address write address read address read address read address p37/clk p33/wrhx p32/wrlx p31/rdx p30/ale p27 to 20/a23 to16 p17 to 10/ad15 to 08 p07 to 00/ad07 to 00 8-bit bus width byte even-number address byte read read 8-bit bus width byte write even-number address byte write read address read address read address invalid write address write address write address read data undefined write data read address read address read address p37/clk p33/wrhx p32/wrlx p31/rdx p30/ale p27 to 20/a23 to 16 p17 to 10/ad15 to 08 p07 to 00/ad07 to 00 * design the external circuit so that data is always read in word mode. even-number address even-number address word read word write read address write address read data write data read address read address write address write address read address read address read address low-speed memory or peripheral circuit can be accessed depending on the setting of the p36/rdy pin or the automatic ready function selection register (arsr). 3.2 external memory access 44 chapter 3: memory MB90580 series (2) ready function when the rye bit of the bus control signal selection register (epcr) is set to '1,' a wait cycle is inserted while an l level signal appears at the r36/rdy pin in the event of an access to an external area. thus, the access cycle can be extended. figure 3.2.1c ready timing chart the f 2 mc-16lx has two types of automatic ready functions for external memory. the automatic ready function automatically inserts one to three wait cycles without an external circuit under the following condi- tions. the function inserts the wait cycles when an access is made to a low-order address external area located between addresses 002000 h and 7fffff h or to a high-order address external area located between addresses 800000 h and ffffff h . this function extends the access cycle. the automatic ready function is activated by setting the lmr1/lmr0 bits (low-order address external area) or the hmr1/hmr0 bits (high-order address external area) of arsr. in addition, the f 2 mc-16lx has another built-in auto- matic ready function for external i/o. this automatic ready function automatically inserts one to three wait cycles without an external circuit when an access is made to an external area located between addresses 0000c0 h and 0000ff h . this function extends the access cycle. this automatic ready function is activated by setting the ior1/ior0 bits of arsr. p37/clk p33/wrhx p32/wrlx p31/rdx p30/ale p27 to 20/a23 to 16 p17 to 10/ad15 to 08 p07 to 00/ad07 to 00 even-number address word read even-number address word write read address write address rdy pin fetch read data write data read address read address write address write address p37/clk p33/wrhx p32/wrlx p31/rdx p30/ale p27-20/a23-16 p17-10/ad15-08 p07-00/ad07-00 cycle extended by automatic ready even-number address word read even-number address word write read address write address write data read address read address write address write address p36/rdy 3.2 external memory access MB90580 series chapter 3: memory 45 when the rye bit of epcr is set to '1,' the wait cycle continues if an l level signal appears at the r36/rdy pin at the end of either automatic ready cycle. (3) hold function when the hde bit of epcr is set to '1,' the external bus hold function by the p34/hrq and p35/hakx pins is enabled. when an h level signal is input to the p34/hrq pin, the hold state starts at the end of the cpu instruction (at the end of processing for one element data item in the case of a string instruction), an l level signal is output from the p35/hakx pin, and the following pins are set to high impedance: ? address output p27/a23 to p20/a16 ? address/data i/o p17/d15 to p00/d00 ? bus control signal p30/ale, p31/rdx, p32/wrlx, p33/wrhx the above function enables the use of an external bus by a device external circuit. when an l level signal is input to the p34/hrq pin, an h level signal is output from the p35/hakx pin, the external pin status is restored, and the cpu resumes operation. in the stop state, no hold request input is accepted. n hold timing (in external bus 16-bit mode) figure 3.2.1d hold timing p37/clk p34/hrq p35/hakx p33/wrhx p32/wrlx 23 to 20/a19 to 16 17 to 10/ad15 to 08 07 to 00/ad07 to 00 p30/ale p31/rdx read cycle hold cycle write cycle (address) read data (address) write data (address) (address) chapter 4: clock and reset 4.1 clock generator the clock generator controls internal clock operation, including such functions as sleep, timer, stop, and pll multiplication. this internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle. a clock based on the source oscillation is called the main clock, and a clock based on the internal vco oscillation is called the pll clock. note: when the operating voltage is 5 v, the osc source oscillation can be between 3 mhz and 16 mhz. the highest operating frequency for the cpu and peripheral resource circuits is 16 mhz, however. normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 mhz is specified. for example, if the source oscillation is 16 mhz, only 1 can be specified as the multiplication factor. the lowest operating frequency of the vco oscillation is 4 mhz, and an oscillation below 4 mhz must not be specified. figure 4.1a clock generator circuit block diagram s q r sq r sq r xl x0 1/2 1/2048 1/4 1/4 1/8 12 3 4 reset interrupt transition to transition to selecting the oscillation selecting the machine clock machine clock pll multiplication time base timer selecting the watch-dog monitoring watch-dog reset hstx stop mode timer or sleep mode stabilization wait time timer timer interval 4.2 reset causes 48 chapter 4: clock and reset MB90580 series 4.2 reset causes when a reset cause occurs, f 2 mc-16lx terminates the currently executing processing and waits for the release of reset signal. a reset can be caused by the following factors: m power-on reset m hardware standby release m watch-dog timer overflow m external reset request via rstx pin m reset request by software right after stop mode release or power on reset, the mcu will wait for the stabilization time before resumption of any activities. when reset occurs, f 2 mc-16lx will stop all operation at once and wait for the release of reset. the content of watchdog timer control register will change according to the reset cause. thus, the cause of previous reset can be known. note: while an external bus is used, the address generated by the device is undefined when a reset cause occurs. all external bus access signals, including rdx and wrx, become inactive. * in stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless of the reset cause. * the oscillation stabilization time for a power-on reset is fixed to 2 18 cycles of source oscillation. for other types of reset, the oscillation stabilization wait time is determined by cs1 and cs0 of the clock selection register. as shown in figure 4.2a, each reset cause has a corresponding flip-flop. the contents of the flip-flop can be obtained by reading the watch-dog timer control register. if identifying the reset cause is required after the reset is released, ensure that the value read from the watch-dog timer control register is processed by software and processing branches to an appropriate program. table 4.2a reset causes reset cause machine clock watch-dog timer oscillation stabilization wait power-on when the power is turned on main clock stop yes hardware standby 'l' level input to hstx pin main clock stop yes watch-dog timer watch-dog timer overflow main clock stop yes external pin 'l' level input to rstx pin previous status maintained previous status maintained no software '0' written to rst bit of stbyc previous status maintained previous status maintained no 4.2 reset causes MB90580 series chapter 4: clock and reset 49 figure 4.2a reset cause bit block diagram figure 4.2b wdtc (watch-dog timer control register) when there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer control register are set. therefore, if an external reset request and a watch-dog reset occur at the same time, both the erst and wrst bits are set to 1. a power-on reset is an exception; while the ponr bit is 1, the values of other bits do not indicate the correct reset causes. therefore, design software so that the other reset cause bit values are ignored while the ponr bit is set to 1. (an asterisk (*) in the table means that the previous value is maintained.) note: a reset cause bit is cleared only by reading the watch-dog timer control register. thus, once a reset occurs, the corresponding reset cause bit remains 1 even if another reset cause occurs. table 4.2b reset cause bits reset cause ponr stbr wrst erst srst power-on 1 hardware standby *1*** watch-dog timer **1** external pin ***1* rst bit ****1 f / f f / f f / f f / f f / f hstx=l?h rstx=l sr q s ss s rr r r q q qq hstx pin rstx pin without periodic clear rst bit set power on power-on hardware standby external reset watch-dog timer stbyc.rst bit delay wtc register wtc register read f 2 mc-16lx internal bus circuit write detection circuit detection circuit release detection circuit request detection circuit reset detection circuit srst wte wt1 wt0 erst wrst ponr address: 0000a8 h read/write initial value bit no. (r) (x) wdtc stbr (w) (1) 6543210 7 (w) (1) (w) (1) (r) (x) (r) (x) (r) (x) (r) (x) 4.3 operation after reset release 50 chapter 4: clock and reset MB90580 series 4.3 operation after reset release when a reset cause is removed, the f 2 mc-16lx immediately outputs the address in which the reset vec- tor is stored, then fetches the reset vector and mode data. the reset vector and mode data are assigned to the four bytes between ffffdc h and ffffdf h . after reset is released, the reset vector and mode data are transferred to the registers by the hardware as described in figure 4.3a. use the mode pin to specify whether to read the reset vector and mode data from internal rom or from external memory. when the mode pin is set to external vector mode, the f 2 mc-16lx reads the reset vector and mode data from external memory. when using the f 2 mc-16lx in single chip mode or internal rom external bus mode, fujitsu recommends specifying internal vector mode. the bus mode after the reset vector and mode data are read is specified by the mode data. figure 4.3a source and destination of reset vector and mode data pcb pc ffffdf h ffffde h ffffdd h ffffdc h memory space mode data reset vector bits 23 to 16 reset vector bits 15 to 8 reset vector bits 7 to 0 f 2 mc-16lx cpu core register reset sequence mode micro rom chapter 5: watchdog timer, timebase timer, and watch timer functions 5.1 outline watch-dog timer the watchdog timer consists of 2-bit counter that uses to carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. the watch-dog timer function enables detection of program surge. if the watch-dog timer is not accessed within the speci- fied time due to, for example, a program surge, the watch-dog timer resets the system. time base timer the timebase timer consists of 18-bit counter and a circuit that control interval interrupts. the timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc.it is counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 2 12 /hclk, 2 14 /hclk, 2 16 /hclk, and 2 19 /hclk. (hclk is the main clock.) note taht the timebase timer uses the main clock, regardless of the mcs bit and scs bit in ckscr. watch timer the watch timer consists of 15-bit counter and a circuit that controls interval interrupts. the watch timer functions as the clock source for the watchdog counter, as the timer for the subclock stabilization wait, and as an interval timer that generates interrupts at a given period. note that the watch timer uses the sub clock, regardless of the mcs bit and scs bit in ckscr. 5.2 block diagram 52 chapter 5: watchdog timer, timebase timer, and watch timer functions MB90580 series 5.2 block diagram figure 5.2a watchdog timer, timebase timer, and watch timer block diagram f 2 mc-16 bus timebase selector clock input timebase timer main clock 2-bit counter watchdog reset to wdgrst from power-on from hardware rstx pin from rst bit of interrupt tbc1 tbtc tbc0 tbr tbie tbof wdtc wt1 wt0 wte ponr stbr wrst erst srst and s q r 2 12 2 14 2 16 2 18 tbtres selector 2 14 2 16 2 17 2 18 of clr generation circuit clr internal reset generation circuit generation standby control circuit stbyc register wtc wdcs sce wtc1 wtc0 wtr wtie wtof and s q r selector watch timer 2 10 2 13 2 14 2 15 wtres 2 10 2 13 2 14 2 15 clock input subclock clock interrupt power-on reset /subclock stop scm and s q r wdtc 5.3 registers and register details MB90580 series chapter 5: watchdog timer, timebase timer, and watch timer functions 53 5.3 registers and register details ponr stbr wrst erst srst wte wt1 wt0 76543 2 10 address : 0000a8 h (r) (r) (r) (r) (r) (w) (w) (w) (x) (x) (x) (x) (x) (1) (1) (1) read/write initial value bit number watch-dog timer control register wdtc address: 0000a9 h reserved tbie tbof tbr tbc1 tbc0 15 14 13 12 11 10 9 8 bit number (-) (-) (-) (r/w) (r/w) (w) (r/w) (r/w) (1) (-) (-) (0) (0) (1) (0) (0) read/write initial value timer base timer control register tbtc address: 0000aa h wdcs wtc2 wtof wtr wtc1 wtc0 76 5 4 321 0 wtc wtie sce bit number watch timer control register (r/w) (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (1) (x) (0) (0) (0) (0) (0) (0) read/write initial value 5.3 registers and register details 54 chapter 5: watchdog timer, timebase timer, and watch timer functions MB90580 series 5.3.1 wdtc (watch-dog timer control register) dont use read-modify-write command to access this register, otherwise malfunction will occur. [bits 7 to 3] ponr, stbr, wrst, erst, and srst these flags indicate the reset causes. the flags are set upon a reset as described in table 5.3.1a. all bits are cleared to '0' after the wdtc register is read. the wdtc register is a read-only register. this is a read-only register. note that during power-on only, the contents of the bits that indicate sources other than power-on are not guaranteed. therefore, software should be designed to ignore the other bits when the ponr bit is "1". (*: the previous value is maintained.) [bit 2] wte while the watch-dog timer is stopped, writing '0' to this bit activates the watch-dog timer. subsequently, writing '0' clears the watch-dog timer counter. writing '1' has no effect. the watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer. '1' is always read from this bit. [bits 1, 0] wt1, wt0 these bits select the watchdog interval time. only the data written when the watchdog timer is started up is valid. data written to these bits at any time other than watchdog startup is ignored. note that the clock that is input to the watchdog timer is selected according to the result of anding the wdcs bit of the wtc and the scm bit of the lpmcr. in other words, if wdcs is set to "1", then the timebase timer output can be selected if the main clock and the pll clock are selected, and the watch timer output can be selected if the subclock is selected. the interval time settings are shown in table 5.3.1a. these bits are write-only bits. table 5.3.1a reset cause registers reset cause ponr stbr wrst erst srst power-on 1 hardware standby *1*** watch-dog timer **1** external pin ***1* rst bit ****1 ponr stbr wrst erst srst wte wt1 wt0 76543 2 10 address : 0000a8 h (r) (r) (r) (r) (r) (w) (w) (w) (x) (x) (x) (x) (x) (1) (1) (1) read/write initial value bit number watch-dog timer control register wdtc 5.3 registers and register details MB90580 series chapter 5: watchdog timer, timebase timer, and watch timer functions 55 table 5.3.1b watchdog timer interval selection bits note: the maximum interval value is the value when the time base counter or the clock counter are not reset during watchdog operation. wdcs/ scm wt1 wt0 interval time (source oscillation: 4 mhz) minimum maximum 1 0 0 approx. 3.58 ms approx. 4.61 ms 1 0 1 approx. 14.33 ms approx. 18.43 ms 1 1 0 approx. 57.23 ms approx. 73.73 ms 1 1 1 approx. 458.75 ms approx. 589.82 ms 0 0 0 approx. 0.109 s approx. 0.141 s 0 0 1 approx. 0.875 s approx. 1.125 s 0 1 0 approx. 1.75 s approx. 2.25 s 0 1 1 approx. 3.5 s approx. 4.5 s 5.3 registers and register details 56 chapter 5: watchdog timer, timebase timer, and watch timer functions MB90580 series 5.3.2 tbtc (time base timer control register) note: dont use read-modify-write command to access this register, otherwise malfunction will occur. [bit 15] reserved this is a reserved bit. when writing data to this register, ensure that '1' is written to this bit. [bit 12] tbie this bit is used to enable interval interrupts based on the time base timer. writing '1' to this bit enables interrupts, and writing '0' disables interrupts. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 11] tbof this is an interrupt request flag for the time base timer. while the tbie bit is '1,' an interrupt request is issued when '1' is written to tbof. this bit is set to '1' for each interval specified with the tbc1 and tbc0 bits. this bit is cleared by writing '0,' by switching to stop or hardware standby mode, or by a reset. writing '1' has no effect. 1' is always read by a read-modify-write instruction. [bit 10] tbr this bit clears all bits of the time base timer counter to '0.' writing '0' clears the time base counter. writing '1' has no effect. '1' is always read from this bit. note: time base timer interrupt should be masked by either tbie bit or ilm bit of cpu before clearing the tbof bit. [bits 9 and 8] tbc1 and tbc0 these bits are used to set the time base timer interval. table 5.3.2a selecting the time base timer interval tbc1 tbc0 interval at 4 mhz source oscillation machine clock cycle 0 0 1.024 ms 2 12 cycle 0 1 4.096 ms 2 14 cycle 1 0 16.384 ms 2 16 cycle 1 1 131.072 ms 2 19 cycle address: 0000a9 h reserved tbie tbof tbr tbc1 tbc0 15 14 13 12 11 10 9 8 bit number (-) (-) (-) (r/w) (r/w) (w) (r/w) (r/w) (1) (-) (-) (0) (0) (1) (0) (0) read/write initial value timer base timer control register tbtc 5.3 registers and register details MB90580 series chapter 5: watchdog timer, timebase timer, and watch timer functions 57 5.3.3 watch timer control register (wtc) [bit 7] wdcs this bit selects whether to use the clock signal from the watch timer or from the timebase timer for the watchdog timer input clock when the main clock and pll clock are selected. when this bit is "0", the clock signal from the watch timer is selected; when this bit is "1", the clock signal from the timebase timer is selected. in short, if wdcs is set to "1", then the timebase timer output can be selected if the main clock and the pll clock are selected, and the watch timer output can be selected if the subclock is selected. this bit is initialized to "1" by a power-on reset. note: when wdcs is set to "1", because the timebase timer output and the watch timer out- put are asynchronous, there is a possibility that the watchdog timer count may advance. therefor, when wdcs is set to "1", it is necessary to clear the watchdog timer before and after changing the clock mode. [bit 6] sce this bit indicates that the subclock oscillation stabilization waiting period has elapsed. when this bit is "0", it indicates that the oscillation stabilization period is currently in progress. the oscillation stabilization period is fixed at 2 14 cycles (subclock). this bit is initialized to "0" by a power-on reset and by stopping. [bit 5] wtie this bit enables interval interrupts by the watch timer. when this bit is set to "1", interrupts are enabled; when set to "0", interrupts are disabled. this bit is initialized to "0" by a reset. this bit can be read and written. [bit 4] wtof this bit is the watch timer interrupt request flag. when the wtie bit is "1", an interrupt request is generated if wtof is set to "1". this bit is set to "1" at the intervals set by the wtc1 and wtc0 bits. this bit is cleared by writing a "0", by switching to stop mode or hardware standby mode, and by a reset. writing "1" to this bit has no meaning. when this bit is read by a read-modify-write instruction, a "1" is read. [bit 3] wtr this bit clears all of the watch timer counter bits to "0". the clock counter is cleared by writing a "0" to this bit. writing "1" to this bit has no meaning. reading this bit returns a "1". [bits 2, 1, 0] wtc2, wtc1, wtc0 these bits set the watch timer interval. the interval settings are shown in table 5.3.3a. these bits are initialized to "000" by a reset. these bits can be read and written. when writing these bits, clear bit 4 (wtof) at the same time. address: 0000aa h wdcs wtc2 wtof wtr wtc1 wtc0 76 5 4 32 1 0 wtc wtie sce bit number watch timer control register (r/w) (r) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (1) (x) (0) (0) (0) (0) (0) (0) read/write initial value 5.3 registers and register details 58 chapter 5: watchdog timer, timebase timer, and watch timer functions MB90580 series table 5.3.3a watch timer interval selection wtc2 wtc1 wtc0 interval time when subclock is 32 khz 0 0 0 15.625 ms 0 0 1 31.25 ms 0 1 0 62.5 ms 0 1 1 0.125 s 1 0 0 0.250 s 1 0 1 0.500 s 1 1 0 1.000 s 11 1 C 5.4 operation MB90580 series chapter 5: watchdog timer, timebase timer, and watch timer functions 59 5.4 operation 5.4.1 watch-dog timer the watch-dog timer function enables detection of program surge. if the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. (1) activation the watch-dog timer is activated by writing '0' to the wte bit of the wtc register while the watch-dog timer is stopped. at the same time, the wt1 and wt0 bits are used to set the watch-dog timer reset interval. only the interval setting specified during activation is valid. (2) watch-dog counter once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the program. writing '0' to the wte bit of the wtc register clears the watch-dog counter. the watch-dog counter consists of a two-bit counter which uses the carry signals of the time base counter as a clock source. therefore, the watch-dog reset time may become shorter than the setting if the time base counter is cleared. figure 5.4.1a is a diagram of the watch-dog timer operation. figure 5.4.1a watch-dog timer operation (3) watch-dog stop once activated, the watch-dog timer is initialized and stopped only by power-on, hardware standby, or reset by watch-dog. reset by an external pin or software merely clears the watch-dog counter without stopping the watch-dog function. (4) others the watch-dog counter is cleared by a reset, transition to sleep or stop mode, or hold acknowledgment signal in addition to writing the wte bit. 00 01 10 00 01 10 11 00 time base watch-dog wte write watch-dog clear watch-dog reset watch-dog activation 5.4.2 time base timer the time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to sta- bilize, and interval timer for generating interrupts at specified intervals. (1) time base counter the time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two. this clock is used to generate the machine clock. while the source oscillation is input, the time base counter keeps counting. the time base counter is cleared by a power-on reset, transition to stop or hardware standby mode, shifting from the main clock to the pll clock through the setting of the mcs bit in the ckscr register, shifting from the main clock to the subclock through the setting of the scs bit in the ckscr register, or writing '0' to the tbr bit of the tbtc register. (2) interval interrupt function interrupts are generated at specified intervals according to the carry signals of the time base counter. the tbof flag is set at the intervals specified with the tbc1 and tbc0 bits of the tbtc register. the flag is written to reference to the time at which the time base timer is cleared last. if a shift is made from the main clock mode to the pll clock mode, the timebase timer is cleared, since it is used as the timer for the pll clock oscillation stabilization waiting period. in addition, if a shift is made from the main clock mode to the subclock mode, the timebase timer is cleared, since it is used as the timer for the main clock oscillation stabilization waiting period. upon transition to stop or hardware standby mode, the time base timer is used as a timer for waiting for the oscillation to stabilize upon recovery. therefore, the tbof flag is immediately cleared upon mode transition. 5.4.3 watch timer the watch timer functions as the clock source for the watchdog counter, as the timer for the subclock stabilization wait, and as an interval timer that generates interrupts at a given period. (1) watch timer the watch timer is a 15-bit counter that counts the source oscillation input which is used to generate the machine clock. the watch timer always continues its counting operation as long as the source oscillation is being input. the watch timer is cleared by: power-on reset, shifting to stop mode or hardware standby mode, and writing "0" to the wtr bit in the wtc register. the watchdog counter and the interval interrupts, both of which utilize the watch timer output, are affected by the watch timer being cleared. (2) interval interrupt function this function generates interrupts at a given period based on the clock counter carry signal. this function sets the wtof flag at a regular interval, which is set by the wtc1 and wtc0 bits in the wdtc register. the timing for the setting of this flag is based on the time when the watch timer was last cleared. if a shift is made to stop mode or hardware standby mode, the wtof flag is cleared at the same time as the mode shift, since the watch timer is used for the oscillation stabilization waiting period during recovery. chapter 6: low power control circuit 6.1 outline the following are the operating modes: pll clock mode, pll sleep mode, pll watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. aside from the pll clock mode, all of the other operating modes are low power consumption modes. in main clock mode and main sleep mode, only the main clock (main osc oscillation clock) and the subclock (sub osc oscillation clock) operate. in these modes, the main clock divided by two is used as the operation clock, the subclock (sub osc oscillation clock) is used as the watch clock, and the pll clock (vco oscillation clock) is stopped. in subclock mode and sub sleep mode, only the subclock (sub osc oscillation clock) operates. the subclock is used as the operation clock, and the main clock and the pll clock are stopped. in pll sleep mode and main sleep mode, only the cpu's operation clock is stopped, all clocks other than the cpu clock operate. in pseudo-watch mode, only the watch timer and the timebase timer operate. in pll watch mode, main watch mode, and sub-watch mode, only the watch timer operates. only the subclock is in operation in this mode; the main clock and the pll clock are stopped. (the difference among pll watch mode, main watch mode, and sub-watch mode is that the operating mode upon recov- ery from an interrupt is pll clock mode, main clock mode, or subclock mode, respectively. there are no differences in the watch mode operations.) the main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power possible. (the difference between main stop mode and sub stop mode is that the operating mode upon recovery from an interrupt is main clock mode or subclock mode, respectively. there are no differences in the stop mode operations.) the cpu intermittent operation function intermittently runs the clock supplied to the cpu when accessing registers, on-chip memory, on-chip resources, and the external bus. processing is possible with lower power consumption by reducing the execution speed of the cpu while supplying a high-speed clock to the on-chip resources. the pll clock multiplier can be selected as either 2, 4, 6, or 8 by setting the cs1 and cs0 bits. the selected clock divided by two is used as the machine clock. the ws1 and ws0 bits can be used to set the main clock oscillation stabilization waiting period for when stop mode and hardware standby mode are released. 6.2 block diagram 62 chapter 6: low power control circuit MB90580 series 6.2 block diagram figure 6.2a low-power consumption control circuit and clock generator f 2 mc-16lx bus subclock main clock cpu clock 0/9/17/33 intermittent scm sleep standby mstp control circuit stop rst cancel hst start peripheral clock main osc stop sub osc stop interrupt request pin high-impedance pin hi-z self-refresh rstx pin internal rst to watchdog timer pll multiplier circuit 1 2 3 4 cpu clock selector 1/2 s subclock switching controller cpu system generation cpu intermittent operation function cycle number selection circuit peripheral generation oscillation wait time self-refresh control circuit internal reset clock input timebase timer 2 4 2 13 2 15 2 18 2 12 2 14 2 16 2 19 ckscr scm scs ckscr mcm mcs ckscr cs1 cs0 lpmcr cg1 cg0 lpmcr slp stp tmd ckscr ws1 ws0 stabilization selector control circuit generation circuit spl ssr rst lpmcr lpmcr clock system clock or rst hstx pin (osc oscillation) (osc oscillation) cycle selection wdgrst 6.3 registers and register details MB90580 series chapter 6: low power control circuit 63 6.3 registers and register details 6.3.1 lpmcr (low power mode control register) [bit 7] stp writing a "1" to this bit changes the mode to pseudo-watch mode (ckscr. mcs = 0 and scs = 1) or stop mode (ckscr. mcs = 1 or scs = 0). writing a "0" to this bit has no effect. this bit is cleared to "0" by a reset, wake-up from watch or stop mode. this bit is a write-only bit. when this bit is read, "0" is always returned. [bit 6] slp writing a "1' to this bit changes the mode to sleep mode. writing a "0" to this bit has no effect. this bit is cleared to "0" by a reset, wake-up from sleep or stop mode. if a "1' is written to both the stp bit and the slp bit simultaneously, the mode changes to either pseudo-watch mode or to stop mode. this bit is a write-only bit. when this bit is read, "0" is always returned. [bit 5] spl when this bit is "0", the level of external pins in watch mode or stop mode is retained. when this bit is "1", the external pins in watch mode or stop mode go to high-impedance. this bit is cleared to "0" by a reset. this bit can be read and written. cg1 cg0 ssr rst 76 5 4 321 0 spl stp slp address: 0000a0 h bit no. (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) lpmcr (w) (0) (w) (1) (r/w) (0) (w) (1) tmd low power mode control register mcs cs1 scs ws0 ws1 mcm address: 0000a1 h read/write initial value bit no. (r) (1) (r/w) (1) (r/w) (1) (r/w) (0) ckscr (r) (1) (r/w) (1) scm (r/w) (1) (r/w) (0) cs0 15 14 13 12 11 10 9 8 clock selection register read/write initial value cg1 cg0 ssr rst 76543210 spl stp slp address: 0000a0 h bit no. (w) (0) (r/w) (0) (r/w) (0) (r/w) (0) lpmcr (w) (0) (w) (1) (r/w) (0) (w) (1) tmd low power mode control register read/write initial value 6.3 registers and register details 64 chapter 6: low power control circuit MB90580 series [bit 4] rst writing a "0" to this bit generates an internal reset signal in three machine cycles. writing a "1' to this bit has no effect. when this bit is read, a "1" is returned. [bit 3] tmd writing a "0" to this bit changes the mode to watch mode. writing a "1" to this bit has no effect. this bit is set to "1" by a reset, wake-up from watch or stop mode. this bit is a write-only bit. when this bit is read, "1" is always returned. [bits 2, 1] cg1, cg0 these bits set the number of clock pause cycles for the cpu intermittent operation function. these bits are initialized to "00" by a reset due to power-on, hardware standby, or a reset by the watchdog timer. these bits are not initialized by resets due to other sources. these bits can be read or written. table 6.3.1a cg bit setting [bit 0] ssr when this bit is set to "1", dramc self-refresh control is performed in sleep (main/pll) mode, watch mode, and stop mode. this bit is cleared to "0" by a refresh. this bit can be read and written. note: ssr has no function if there is no dramc on chip. cg1 cg0 number of cpu clock pause cycles 0 0 0 cycles (cpu clock = resource clock) 0 1 9 cycles (cpu clock: resource clock = 1: approximately 3 to 4) 1 0 17 cycles (cpu clock: resource clock = 1: approximately 5 to 6) 1 1 33 cycles (cpu clock: resource clock = 1: approximately 9 to 10) 6.3 registers and register details MB90580 series chapter 6: low power control circuit 65 6.3.2 ckscr (clock selection register) [bit 15] scm this bit indicates whether the main clock or the subclock is selected as the machine clock. when this bit is "0", it indicates that the subclock is selected; when this bit is "1", it indicates that the main clock is selected. if scs = 0 and scm = 1, it indicates that the main clock oscillation stabilization waiting period is in progress. [bit 14] mcm this bit indicates whether the main clock or the pll clock is selected as the machine clock. when this bit is "0", it indicates that the pll clock is selected; when this bit is "1", it indicates that the main clock is selected. if mcs = 0 and mcm = 1, it indicates that the pll clock oscillation stabilization waiting period is in progress. note that the pll clock oscillation stabilization waiting period is fixed at 2 12 main clock cycles. [bits 13, 12] ws1, ws0 these bits set the main clock oscillation stabilization waiting period upon wake-up from stop mode or hardware standby mode is released. these bits are initialized to "11" by a power-on reset; these bits are not initialized by a reset due to other sources. these bits can be read and written. table 6.3.2a ws bit settings [bit 11] scs this bit selects either the main clock or the subclock as the machine clock. when a "0" is written to this bit, the subclock is selected; when a "1" is written to this bit, the main clock is selected. if a "1" is written to this bit while it is "0", the oscillation stabilization waiting period for the main clock is generated; therefore, the timebase timer is automatically cleared. in addition, the subclock (as is) is used for the operation clock when the subclock is selected. (when the source oscillation is 32 khz, the operation clock is 32 khz.) when scs and mcs are both set to "0", scs takes priority and the subclock is selected. this bit is initialized to "1" by a reset due to power-on, hardware standby, the watchdog timer, an external source, or software. ws1 ws0 oscillation stabilization waiting period (source oscillation at 4 mhz) 0 0 no oscillation stabilization waiting period 0 1 approx. 1.02 ms (count of 2 14 of the source oscillation) 1 0 approx. 8.19 ms (count of 2 16 of the source oscillation) 1 1 approx. 65.54 ms (count of 2 18 of the source oscillation) mcs cs1 scs ws0 ws1 mcm address: 0000a1 h read/write initial value bit no. (r) (1) (r/w) (1) (r/w) (1) (r/w) (0) ckscr (r) (1) (r/w) (1) scm (r/w) (1) (r/w) (0) cs0 15 14 13 12 11 10 9 8 clock selection register 6.3 registers and register details 66 chapter 6: low power control circuit MB90580 series [bit 10] mcs this bit selects either the main clock or the pll clock as the machine clock. when a "0" is written to this bit, the pll clock is selected; when a "1" is written to this bit, the main clock is selected. if a "0" is written to this bit while it is "1", the oscillation stabilization waiting period for the pll clock is generated; therefore, the timebase timer is automatically cleared. note that the pll clock oscillation stabilization waiting period is fixed at 2 12 main clock cycles. in addition, the main clock divided by two is used for the operation clock when the main clock is selected. (when the source oscillation is 4 mhz, the operation clock is 2 mhz.) this bit is initialized to "1" by a reset due to power-on, hardware standby, or the watchdog timer. [bits 9, 8] cs1, cs0 these bits select the pll clock multiplier. these bits are not initialized by a reset initiated by an external pin or the rst bit. these bits are initialized to "00" by a reset due to power-on, hardware standby, and the watchdog timer. writing to these bits is suppressed when the mcs bit is "0". set the mcs bit to "1" (main clock mode) first and then overwrite the cs bits. these bits can be read and written. table 6.3.2b cs bit settings cs1 cs0 machine clock (source oscillation at 4 mhz) 0 0 4 mhz (operation frequency = osc oscillation frequency) 01 8 mhz (operation frequency = osc oscillation frequency 2) 1 0 12 mhz (operation frequency = osc oscillation frequency 3) 1 1 12 mhz (operation frequency = osc (3 mhz) 4) 6.4 operations MB90580 series chapter 6: low power control circuit 67 6.4 operations the status of each chip block in each operating mode is shown in table 6.4a table 6.4a low power consumption mode operating statuses transition condition sub oscillation main oscillation clock cpu peripheral s pins exit method subclock scs=0 mcs=x operating stopped operating operating operating operating reset interrupt sub sleep scs=0 mcs=x slp=1 operating stopped operating stopped operating operating reset interrupt main sleep scs=1 mcs=1 slp=1 operating operating operating stopped operating operating reset interrupt pll sleep scs=1 mcs=0 slp=1 operating operating operating stopped operating operating reset interrupt pseudo- watch (spl=0) scs=1 mcs=0 stp=1 operating operating stopped stopped stopped main- tained reset interrupt pseudo- watch (spl=1) scs=1 mcs=0 stp=1 operating operating stopped stopped stopped hi-z reset interrupt watch (spl=0) scs=x mcs=x tmd=0 operating stopped stopped stopped stopped main- tained reset interrupt watch (spl=1) scs=x mcs=x tmd=0 operating stopped stopped stopped stopped hi-z reset interrupt stop (spl=0) mcs=1 or scs=0 stp=1 stopped stopped stopped stopped stopped main- tained reset interrupt stop (spl=1) mcs=1 or scs=0 stp=1 stopped stopped stopped stopped stopped hi-z reset interrupt hard- ware standby hstx=l stopped stopped stopped stopped stopped hi-z hstx=h 6.4 operations 68 chapter 6: low power control circuit MB90580 series 6.4.1 sleep mode l transition to sleep mode the standby control circuit is set to sleep mode by writing a "1" to the slp bit, a "1' to the tmd bit, and a "0" to the stp bit in the low power consumption mode control register. in sleep mode, only the clock sup- plied to the cpu is stopped; in this mode, the cpu stops, but the peripheral circuits continue to operate. if an interrupt request is generated when the "1" is written to the slp bit, the standby control circuit does not go into sleep mode. in this case, if the cpu is not accepting interrupts, the next instruction is executed; if the cpu is accepting interrupts, processing branches immediately to the interrupt processing routine. the contents of the accumulator and other dedicated registers, as well as the contents of ram, are maintained in sleep mode. l releasing sleep mode the standby control circuit is used for wake-up from sleep mode when a reset signal is input or when an interrupt is generated. if a wake-up from sleep mode was done by a reset source, the device enters the reset state after wake-up from sleep mode is completed. if an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in sleep mode, the standby control circuit is used for wake-up from sleep mode. once wake-up from sleep mode is completed, the interrupt is handled in the normal manner. if the settings of the i flag, ilm bits, and the interrupt control register (icr) are all set so that the interrupt is accepted, then the cpu executes inter- rupt processing. if the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the instruction that put the device into sleep mode. 6.4.2 pseudo-watch mode l transition to pseudo-watch mode the standby control circuit is set to pseudo-watch mode by writing a "1" to the scs bit and a "0" to the mcs bit in the clock selection register, and a "1" to the tmd bit and a "1" to the stp bit in the low power consumption mode control register. in pseudo-watch mode, all clocks stop, except for the source oscillation (main and sub), the watch timer, and the timebase timer. practically all chip functions cease. in addition, the spl bit in the low power consumption mode control register can be used to control whether i/o pins maintain their previous states or go to high impedance state in pseudo-watch mode. if an interrupt request is generated when the "1" is written to the stp bit, the standby control circuit does not shift to pseudo-watch mode. the contents of the accumulator and other dedicated registers, as well as the contents of ram, are hold in pseudo-watch mode. l exit from pseudo-watch mode the standby control circuit is used for exit from pseudo-watch mode when a reset signal is input or when an interrupt is generated. if an exit from pseudo-watch mode was performed by a reset source, the device enters the reset state after exit from pseudo-watch mode. when recovering from pseudo-watch mode, the standby control circuit is activated first for exit from pseudo-watch mode, and then begins waiting for the pll clock oscillation stabilization wait time to elapse. therefore, even if the exit from of pseudo-watch mode is due to a reset source, the main clock is used for the reset sequence. if an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in pseudo-watch mode, the standby control circuit is activated for exit from pseudo-watch mode. once exit from pseudo-watch mode is completed, the interrupt is handled in the normal manner. if the settings of the i flag, ilm bits, and the interrupt control register (icr) are all set so that the interrupt is accepted, then the cpu executes interrupt processing. if the settings do not permit the interrupt to be accepted, then 6.4 operations MB90580 series chapter 6: low power control circuit 69 processing resumes from the instruction that follows the last instruction that put the device into pseudo-watch mode. 6.4.3 watch mode l transition to watch mode the standby control circuit is set to watch mode by writing a "0" to the tmd bit in the low power con- sumption mode control register. in watch mode, all clocks stop, except for the sub-source oscillation and the watch timer. practically all chip functions cease. in addition, the spl bit in the low power consumption mode control register can be used to control whether i/o pins maintain their previous states or go to high impedance state in watch mode. if an interrupt request is generated when the "1" is written to the tmd bit, the standby control circuit does not shift to watch mode. the contents of the accumulator and other dedicated registers, as well as the contents of ram, are maintained in watch mode. l exit from watch mode the standby control circuit is used for exit from watch mode when a reset signal is input or when an interrupt is generated. if watch mode was released by a reset source, the device enters the reset state after exit from watch mode. when recovering from sub-watch mode, the standby control circuit is activated first for exit from watch mode, and then immediately enters subclock mode. therefore, even if the wake-up from sub-watch mode is due to a reset source, the sub-clock is used for the reset sequence. when recovering from main watch mode or pll watch mode, the standby control circuit is activated first for exit from watch mode, and then begins waiting for the main clock oscillation stabilization period to elapse. therefore, even if the exit from watch mode is due to a reset source, the sub-clock is used for the reset sequence. if an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in watch mode, the standby control circuit is activated for exit from watch mode. once exit from watch mode is completed, the interrupt is handled in the normal manner. if the settings of the i flag, ilm bits, and the interrupt control register (icr) are all set so that the interrupt is accepted, then the cpu executes interrupt processing. if the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into watch mode. 6.4.4 stop mode l transition to stop mode the standby control circuit is set to stop mode by writing a "0" to the scs bit and a "1" to the mcs bit in the clock selection register, and a "1" to the stp bit in the low power consumption mode control register. in stop mode, all oscillation sources (sub and main) stop. all chip functions cease. as a result, data can be retained with the barest minimum of power consumption. in addition, the spl bit in the lpmcr can be used to control whether i/o pins maintain their previous states or go to high impedance state in stop mode. if an interrupt request is generated when the "1" is written to the stp bit, the standby control circuit does not go into stop mode. the contents of the accumulator and other dedicated registers, as well as the contents of ram, are maintained in stop mode. 6.4 operations 70 chapter 6: low power control circuit MB90580 series l exiting stop mode the standby control circuit releases stop mode when a reset signal is input or when an interrupt is generated. if stop mode was released by a reset source, the device enters the reset state after stop mode is released. when recovering from sub-stop mode, the standby control circuit first begins waiting for the sub-clock oscillation stabilization waiting period to elapse, and then exits stop mode. therefore, even if the exit from stop mode is due to a reset source, the reset sequence is executed after the sub-clock oscillation stabilization waiting period elapses. when recovering from main stop mode, the standby control circuit first begins waiting for the main clock oscillation stabilization waiting period to elapse, and then exits stop mode. therefore, even if the exit from stop mode is due to a reset source, the reset sequence is executed after the main clock oscillation stabilization waiting period elapses. if an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in stop mode, the standby control circuit exits stop mode. after exit from sub-stop mode, and after the sub-clock oscillation stabilization waiting period has elapsed, the interrupt is handled in the normal man- ner. if the settings of the i flag, ilm bits, and the interrupt control register (icr) are all set so that the inter- rupt is accepted, then the cpu executes interrupt processing. if the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into stop mode. after exit from main stop mode, and after the main clock oscillation stabilization waiting period (specified by the ws1 and ws0 bits in the ckscr) has elapsed, the interrupt is handled in the normal manner. if the settings of the i flag, ilm bits, and the interrupt control register (icr) are all set so that the interrupt is accepted, then the cpu executes interrupt processing. if the settings do not permit the interrupt to be accepted, then processing resumes from the instruction that follows the last instruction that put the device into stop mode. 6.4.5 hardware standby mode l transition to hardware standby mode by setting the hstx pin to low level, it is possible to set the standby control circuit to hardware standby mode, regardless of the current status. in hardware standby mode, oscillation stops and all i/o pins go to high impedance as long as the hstx pin is low, regardless of any other statuses, including resets. although the contents of internal ram are maintained in hardware standby mode, the accumulator and other dedicated registers are all initialized. l waking up from hardware standby mode wake-up from hardware standby mode can only be executed through the hstx pin. when the hstx pin goes high, the standby control circuit is activated for wake-up from hardware standby mode and the device begins waiting for oscillation stabilization after the internal reset signal is enabled. after the main clock oscillation stabilization waiting period elapses, the standby control circuit releases the internal reset, after which the cpu begins execution, starting from the reset sequence. 6.4.6 cpu intermittent operation function the cpu intermittent operation function regularly stops the clock supplied to the cpu for a given period of time when accessing registers, on-chip memory, on-chip resources, and the external bus, delaying the start of the internal bus cycle. processing is possible with lower power consumption by reducing the execution speed of the cpu while supplying a high-speed clock to the on-chip resources. the cg1 and cg0 bits select the number of pause cycles in the clock supplied to the cpu. note that the same clock is used for external bus operations as for resources. 6.4 operations MB90580 series chapter 6: low power control circuit 71 in addition, the instruction execution time when the cpu intermittent operation function is used can be calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource, and external bus access multiplied by the number of pause cycles) to the normal execution time. 6.4.7 setting the main clock oscillation stabilization waiting period the ws1 and ws0 bits can be used to set the main clock oscillation stabilization waiting period for wake- up from stop mode and hardware standby mode. the oscillation stabilization waiting period should be set in accordance with the type and characteristics of the oscillation circuit and oscillator connected to the x0 and x1 pins. these bits are not initialized in the event of a reset, except for a power-on reset. if a power-on reset is generated, these bits are initialized to "11". therefore, when power is first applied, the main clock oscil- lation stabilization waiting period is set to approximately a count of 2 18 pulses of the source oscilla- tion. 6.4.8 switching the machine clock l main clock/pll clock switching switching between the main clock and the pll clock is accomplished by writing to the mcs bit in the ckscr register. if the mcs bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the pll clock, once the pll clock oscillation stabilization waiting period passes (2 11 machine clocks). if the mcs bit is overwritten from a "0" to a "1", the machine clock switches from the pll clock to the main clock, at the point when the edges of the pll clock and the main clock match (after 1 to 8 pll clocks). because the machine clock does not switch immediately after the mcs bit is overwritten, when per- forming operations on resources that depend on the machine clock, always reference the mcm bit and make sure that the machine clock was switched before performing the operation on the resource. l main clock/sub-clock switching switching between the main clock and the sub-clock is accomplished by writing to the scs bit in the ckscr register. if the scs bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the sub- clock when the sub-clock edge is detected. if the scs bit is overwritten from a "0" to a "1", the machine clock switches from the sub-clock to the main clock after the main clock oscillation stabilization waiting period elapses. because the machine clock does not switch immediately after the scs bit is overwritten, when performing operations on resources that depend on the machine clock, always reference the scm bit and make sure that the machine clock was switched before performing the operation on the resource. peripheral clock cpu clock intermittent operation pause cycle internal bus activation cycle 6.4 operations 72 chapter 6: low power control circuit MB90580 series l machine clock initialization the mcs bit and the scs bit are not initialized by a reset caused by an external pin or the rst bit. after other types of resets, these bits are each initialized to "1". figure 6.4.8a and figure 6.4.8b show the clock selection state diagram. figure 6.4.8a clock selection state transition diagram (1) power on pll4 multiplier scs=1, msc=0 scm=1,mcm=0 cs1/0=11 pll3 multiplier scs=1, msc=0 scm=1,mcm=0 cs1/0=10 pll2 multiplier scs=1, msc=0 scm=1,mcm=0 cs1/0=01 pll1 multiplier scs=1, msc=0 scm=1,mcm=0 cs1/0=00 pll3 t main scs=0ormsc=1 scm=1,mcm=0 cs1/0=10 pll2 t main scs=0ormsc=1 scm=1,mcm=0 cs1/0=01 pll1 t main scs=0ormsc=1 scm=1,mcm=0 cs1/0=00 main t pllx scs=1, msc=0 scm=1,mcm=1 cs1/0=xx pll4 t main scs=0ormsc=1 scm=1,mcm=0 cs1/0=11 main t sub scs=1, msc=x mcm=1 scm=1 sub t pllx scs=1, msc=0 scm=0,mcm=1 cs1/0=xx main scs=1, msc=1 scm=1,mcm=1 cs1/0=xx (1) (7) (7) (7) (9) (8) (8) (7) (8) (8) (6) (6) (5) (6) (6) (2) (3) (4) (1) mcs bit clear and scs bit set (2) completion of pll clock oscillation stabilization wait and cs1/0 = 00 (3) completion of pll clock oscillation stabilization wait and cs1/0 = 01 (4) completion of pll clock oscillation stabilization wait and cs1/0 = 10 (5) completion of pll clock oscillation stabilization wait and cs1/0 = 11 (6) mcs bit set and scs bit clear (7) pll clock and main clock synchronization timing and scs = 1 (8) pll clock and main clock synchronization timing and scs = 0 (9) completion of main clock oscillation stabilization wait mcs = 0 6.4 operations MB90580 series chapter 6: low power control circuit 73 figure 6.4.8b clock selection state transition diagram (2) 6.4.9 state transition figure 6.4.9a to figure 6.4.9d show the state transitions in low power consumption mode. in order to keep the state transition diagrams simple, they depict simultaneously occurring events as occurring in stages. in actuality, however, state transitions occur immediately. for example, when mcs is set to "1" and slp is set to "1" simultaneously in pll clock mode, the state transition diagrams show the mode changing once to pm transition mode and then to pm transition sleep, but in actuality, the mode changes immediately from pll clock mode to pm transition sleep. in addition, when a reset occurs in sub sleep mode, the state transition diagrams show the mode changing once to sub mode and then to the main oscillation stabilization period, but in actuality, the mode shifts immediately from sub sleep mode to the main oscillation stabilization period. power on sub scs=0 scm=0 mcm=1 sub t main scs=1 scm=0 mcm=1 main t sub scs=0 scm=1 mcm=1 main t pllx scs=1, msc=0 scm=1, mcm=1 cs1/0=xx pllx t sub scs=0, msc=x scm=1,mcm=0 cs1/0=xx main scs=1, msc=1 scm=1 mcm=1 (1) (5) (6) (4) (2) (3) (1) scs bit clear (2) subclock edge detection timing (3) scs bit set (4) completion of main clock oscillation stabilization wait and mcs = 1 (5) pll clock and main clock synchronization timing and scs = 0 (6) completion of main clock oscillation stabilization wait and mcs = 0 6.4 operations 74 chapter 6: low power control circuit MB90580 series mcs: mcs bit (clock selection register) (pll clock mode is selected when mcs = 0) scs: scs bit (clock selection register) (sub-clock mode is selected when scs = 0) stp: stp bit (low power consumption mode register) (sleep mode is selected when slp = 0) slp: slp bit (low power consumption mode register) (sleep mode is selected when slp = 0) tmd: tmd bit (low power consumption mode register) (watch mode is selected when tmd = 0) mcm: mcm bit (clock selection register) (pll clock is in use when mcm = 0) scm: scm bit (clock selection register) (sub-clock is in use when scm = 0) scd: sub-clock oscillation stopped (sub-clock oscillation is stopped when scd = 1) mcd: main clock oscillation stopped (main clock oscillation is stopped when mcd = 1) pcd: pll clock oscillation stopped (pll clock oscillation is stopped when pcd = 1) table 6.4.9a list of transition conditions state before transition transition conditions state after transition power on 01 main oscillation stabilization waiting period completed main mode main oscillation stabili- zation 05 main oscillation stabilization waiting period completed main mode main mode 06 scs = 0 written ms transition mode 07 scs = 1 ?mcs = 0 written mp transition mode 31 tmd = 1?stp = 0?slp = 1 written main sleep 32 tmd = 0 written main watch transition 33 tmd = 1?stp = 1 written main stop pll mode 21 scs = 0 written ps transition mode 20 scs = 1?mcs = 1 written pm transition mode 59 tmd = 1?stp = 0?slp = 1 written pll sleep 58 tmd = 0 written pll watch transition p 57 tmd = 1?stp = 1 written pseudo-watch transition sub mode 10 scs = 1?mcs = 1 written sm transition mode 12 scs = 1?mcs = 0 written sp transition mode 11 reset initiated main oscillation stabiliza- tion 42 tmd = 1?stp = 0?slp = 1 written sub-sleep 43 tmd = 0 written sub-watch 44 tmd = 1?stp = 1 written sub-stop pm transition mode 13 pll ? main switching timing wait completed main mode 38 tmd = 1?stp = 0?slp = 1 written pm transition sleep 39 tmd = 0 written and pll ? main switching timing wait completed main watch transition 40 tmd = 1 and stp = 1 written and pll ? main switch- ing timing wait completed main stop 6.4 operations MB90580 series chapter 6: low power control circuit 75 sm transition mode 02 main oscillation stabilization waiting period completed main mode 03 reset initiated or interrupt main oscillation stabiliza- tion 04 scs = 0 written sub mode 27 tmd = 1?stp = 0?slp = 1 written sm transition sleep 28 tmd = 0 and main oscillation stabilization waiting period completed main watch 29 tmd = 1 and stp = 1 written and main oscillation sta- bilization waiting period completed main stop mp transition mode 16 pll oscillation stabilization waiting period completed pll mode 14 scs = 1?mcs = 1 written main mode 15 scs = 0 written ms transition mode 68 tmd = 1?stp = 0?slp = 1 written mp transition sleep 70 tmd = 0 written pll watch transition m 69 tmd = 1?stp=1 written pseudo-watch mode sp transition mode 17 main oscillation stabilization waiting period completed mp transition mode 18 mcs = 1 written sm transition mode 19 reset initiated main oscillation stabiliza- tion 75 tmd = 1?stp = 0?slp = 1 written sp transition sleep 76 tmd = 0 written pll watch 78 tmd = 1 and stp = 1 written and main oscillation sta- bilization waiting period completed pseudo-watch mode ms transition mode 09 main ? sub-clock switching timing wait completed sub mode 08 reset initiated main mode 51 tmd = 1?stp = 0?slp = 1 written ms transition sleep 52 tmd = 0 written and main ? sub switching wait com- pleted sub watch 53 tmd = 1 and stp = 1 written and main ? sub switch- ing wait completed sub mode ps transition mode 23 pll ? main clock switching timing wait completed ms transition mode 22 scs = 1 written pm transition mode 56 tmd = 1?stp = 0?slp = 1 written ps transition sleep main sleep 26 interrupt or reset initiated main mode sm transition sleep 24 main oscillation stabilization waiting period completed main sleep 25 interrupt or reset initiated sm transition mode pm transition sleep 34 pll ? main clock switching timing wait completed main sleep 35 interrupt or reset initiated pm transition mode pll sleep 63 interrupt or reset initiated pll mode mp transition sleep 66 pll oscillation stabilization waiting period completed pll sleep 67 interrupt or reset initiated mp transition mode sp transition sleep 73 main oscillation stabilization waiting period completed mp transition sleep 74 interrupt or reset initiated sp transition mode sub-sleep 46 interrupt or reset initiated sub mode table 6.4.9a list of transition conditions (continued) state before transition transition conditions state after transition 6.4 operations 76 chapter 6: low power control circuit MB90580 series ms transition sleep 49 main ? sub-clock switching timing wait completed sub-sleep 50 interrupt or reset initiated ms transition mode ps transition sleep 54 pll ? main clock switching timing wait completed ms transition sleep 55 interrupt or reset initiated ps transition mode main watch 30 interrupt or reset initiated sm transition mode main watch transition 36 main ? sub-clock switching timing wait completed main watch 37 interrupt or reset initiated main mode pll watch 77 interrupt or reset initiated sp transition mode pll watch transition m 72 main ? sub-clock switching timing wait completed pll watch 71 interrupt or reset initiated mp transition mode pll watch transition p 65 pll ? main clock switching timing wait completed pll watch transition m 64 interrupt or reset initiated pll mode sub watch 47 interrupt or reset initiated sub mode main stop 41 interrupt or reset initiated main oscillation stabiliza- tion pseudo-watch 62 interrupt or reset initiated mp transition mode pseudo-watch transi- tion 61 pll ? main clock switching timing wait completed pseudo-watch mode 60 interrupt or reset initiated pll mode sub stop 48 interrupt sub oscillation stabiliza- tion 79 reset initiated main oscillation stabiliza- tion sub oscillation stabili- zation 45 subclock oscillation stabilization waiting period com- pleted sub mode 80 reset initiated main oscillation stabiliza- tion table 6.4.9a list of transition conditions (continued) state before transition transition conditions state after transition 6.4 operations MB90580 series chapter 6: low power control circuit 77 figure 6.4.9a low power consumption mode transition diagram a state transition diagrams power-on reset scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 main mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 pm transition mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 sm transition mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 ms transition mode scs=1, mcs=x, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 mp transition mode scs=1, mcs=0, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=0 pll mode scs=1, mcs=0, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 sub mode scs=0, mcs=x, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=1, pcd=1 sp transition mode scs=1, mcs=0, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 ps transition mode scs=1, mcs=x, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 main oscillation stabilization period 01 02 03 04 05 06 08 09 11 12 19 18 17 15 07 14 13 20 16 21 22 23 10 6.4 operations 78 chapter 6: low power control circuit MB90580 series figure 6.4.9b low power consumption mode transition diagram b sm transition sleep scs=1, mcs=1, stp=0, slp=1, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 sm transition mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 pm transition sleep scs=1, mcs=1, stp=0, slp=1, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 main sleep scs=1, mcs=1, stp=0, slp=1, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 main watch scs=1, mcs=1, stp=0, slp=0, tmd=0 scm=0, mcm=1, scd=0, mcd=1, pcd=1 main watch transition scs=1, mcs=1, stp=0, slp=0, tmd=0 scm=1, mcm=1, scd=0, mcd=0, pcd=1 main stop scs=1, mcs=1, stp=1, slp=0, tmd=1 scm=1, mcm=1, scd=1, mcd=1, pcd=1 scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 main mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 pm transition mode scs=1, mcs=1, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 main oscillation stabilization time 25 24 27 26 28 30 05 32 37 39 36 34 03 20 16 41 40 33 31 35 38 29 6.4 operations MB90580 series chapter 6: low power control circuit 79 figure 6.4.9c low power consumption mode transition diagram c sub mode scs=0, mcs=x, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=1, pcd=1 sub sleep scs=0, mcs=x, stp=0, slp=1, tmd=1 scm=0, mcm=1, scd=0, mcd=1, pcd=1 ms transition sleep scs=0, mcs=x, stp=0, slp=1, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 sub watch scs=0, mcs=x, stp=0, slp=0, tmd=0 scm=0, mcm=1, scd=0, mcd=1, pcd=1 pm transition sleep scs=0, mcs=x, stp=0, slp=1, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 scs=1, mcs=x, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 sub stop scs=0, mcs=x, stp=1, slp=0, tmd=1 scm=0, mcm=1, scd=1, mcd=1, pcd=1 pm transition mode scs=0, mcs=x, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 main oscillation stabilization time 42 45 46 80 43 47 79 44 53 23 52 49 54 55 56 48 51 50 scs=0, mcs=x, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=1, pcd=1 sub oscillation stabilization time ms transition mode scs=0, mcs=x, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 6.4 operations 80 chapter 6: low power control circuit MB90580 series figure 6.4.9d low power consumption mode transition diagram d pll mode scs=1, mcs=0, stp=0, slp=0, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 pll sleep scs=1, mcs=0, stp=0, slp=1, tmd=1 scm=1, mcm=0, scd=0, mcd=0, pcd=0 ms transition sleep scs=1, mcs=0, stp=0, slp=1, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=0 sp transition mode scs=1, mcs=0, stp=0, slp=0, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 scs=1, mcs=0, stp=1, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=1 pll watch scs=1, mcs=0, stp=0, slp=0, tmd=0 scm=0, mcm=1, scd=0, mcd=1, pcd=1 pseudo-watch mode 59 60 63 61 65 58 71 78 16 66 70 76 77 68 67 scs=1, mcs=0, stp=1, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=0 pseudo-watch transition mp transition mode scs=10, mcs=0, stp=0, slp=0, tmd=1 scm=1, mcm=1, scd=0, mcd=0, pcd=0 sp transition sleep scs=1, mcs=0, stp=0, slp=1, tmd=1 scm=0, mcm=1, scd=0, mcd=0, pcd=1 scs=1, mcs=0, stp=0, slp=0, tmd=0 scm=1, mcm=0, scd=0, mcd=0, pcd=0 pll watch transition p scs=1, mcs=0, stp=0, slp=0, tmd=0 scm=1, mcm=1, scd=0, mcd=0, pcd=1 pll watch transition m 57 62 69 17 74 75 73 72 chapter 7: interrupt 7.1 outline the f 2 mc-16lx has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. there are four types of interrupt functions: l hardware interrupt: .................................... interrupt processing due to an internal resource event l software interrupt: ..................................... interrupt processing due to a software event occurrence instruction l extended intelligent i/o service (ei 2 os): ... transfer processing due to an internal resource event l exception: .................................................. termination due to an operation exception 7.2 causes of interrupt 82 chapter 7: interrupt MB90580 series 7.2 causes of interrupt m : the interrupt request flag is cleared by the iios interrupt clear signal. : the interrupt request flag is cleared by the iios interrupt clear signal. a stop request is available. : the interrupt request flag is not cleared by the iios interrupt clear signal. note: for a resource with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the iios interrupt clear signal. table 7.2a interrupt causes, interrupt vectors, and interrupt control registers interrupt cause iios clear interrupt vector interrupt control register number address number address reset # 08 ffffdc h int9 instruction # 09 ffffd8 h exception # 10 ffffd4 h a/d converter m # 11 ffffd0 h icr00 0000b0 h time base timer # 12 ffffcc h dtp0 (external 0) / uart3 reception completion m # 13 ffffc8 h icr01 0000b1 h dtp1 (external 1) / uart4 reception completion m # 14 ffffc4 h dtp2 (external 2) / uart3 transmission completion m # 15 ffffc0 h icr02 0000b2 h dtp3 (external 3) / uart4 transmission completion m # 16 ffffbc h dtp4 - 7 (external 4 - 7) m # 17 ffffb8 h icr03 0000b3 h output compare (channel 1) m # 18 ffffb4 h uart2 reception completion m # 19 ffffb0 h icr04 0000b4 h uart1 reception completion m # 20 ffffac h input capture (channel 3) m # 21 ffffa8 h icr05 0000b5 h input capture (channel 2) m # 22 ffffa4 h input capture (channel 1) m # 23 ffffa0 h icr06 0000b6 h input capture (channel 0) m # 24 ffff9c h 8/16-bit ppg0 counter borrow # 25 ffff98 h icr07 0000b7 h 16-bit reload timer 2 - 0 m # 26 ffff94 h time prescalar # 27 ffff90 h icr08 0000b8 h output compare (channel 0) m # 28 ffff8c h uart2 transmission completion m # 29 ffff88 h icr09 0000b9 h pwc timer m # 30 ffff84 h uart1 transmission completion m # 31 ffff80 h icr10 0000ba h 16-bit free run timer overflow m # 32 ffff7c h uart0 transmission completion m # 33 ffff78 h icr11 0000bb h 8/16-bit ppg1 counter borrow # 34 ffff74 h iebus reception completion # 35 ffff70 h icr12 0000bc h iebus transmission completion # 37 ffff68 h icr13 0000bd h uart0 reception completion # 39 ffff60 h icr14 0000be h reserved # 41 ffff58 h icr15 0000bf h delayed interrupt # 42 ffff54 h 7.3 interrupt vector MB90580 series chapter 7: interrupt 83 7.3 interrupt vector table 7.3a MB90580 interrupt assignment table (1/2) software interrupt instruction vector address l vector address m vector address h mode register interrupt no. hardware interrupt int 0 fffffc h fffffd h fffffe h unused #0 none int 7 ffffe0 h ffffe1 h ffffe2 h unused #7 none int 8 ffffdc h ffffdd h ffffde h ffffdf #8 (reset vector) int 9 ffffd8 h ffffd9 h ffffda h unused #9 none int 10 ffffd4 h ffffd5 h ffffd6 h unused #10 7.4 hardware interrupt 84 chapter 7: interrupt MB90580 series 7.4 hardware interrupt 7.4.1 overview in response to an interrupt request signal from an internal resource, the cpu pauses current program execution and transfers control to the interrupt processing program defined by the user. this function is called the hardware interrupt function. a hardware interrupt occurs when relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register of ps of the cpu, and hardware reference to the i flag value in ps. the cpu performs the following processing when a hardware interrupt occurs: saves the values in the pc, ps, ah, al, pcb, dtb, adb, and dpr registers of the cpu to the system stack. sets ilm in the ps register. the currently requested interrupt level is automatically set. fetches the corresponding interrupt vector value and branches to the processing indicated by that value. 7.4.2 structure hardware interrupts are handled by the following three sections: internal resources ...................interrupt enable and request bits: used to control interrupt requests from resources. interrupt controller...................icr:assigns interrupt levels and determines the priority levels of simultaneously requested interrupts. cpu ........................................i and ilm:used to compare the requested and current interrupt levelsand to identify the interrupt enable status. microcode:interrupt processing step the status of these sections are indicated by the resource control registers for internal resources, the icr for the interrupt controller, and the ccr value for the cpu. to use a hardware interrupt, set the three sections beforehand by using software. the interrupt vector table referenced during interrupt processing is assigned to addresses fffc h to ffffff h in memory. these addresses are shared with software interrupts. 7.4.3 operation an internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. the interrupt request flag indicates whether an interrupt request exists, and the inter- rupt enable flag indicates whether the relevant internal resource requests an interrupt to the cpu. the interrupt request flag is set when an event occurs that is unique to the internal resource. when the interrupt enable flag indicates "enable," the resource issues an interrupt request to the interrupt controller. when two or more interrupt requests are received at the same time, the interrupt controller compares the interrupt levels (il) in icr, selects the request at the highest level (the smallest il value), then reports that request to the cpu. if multiple requests are at the same level, the interrupt controller selects the request with the lowest interrupt number. the relationship between the interrupt requests and icrs is determined by the hardware. the cpu compares the received interrupt level and the ilm in the ps register. if the interrupt level is smaller than the ilm value and the i bit of the ps register is set to 1, the cpu activates the interrupt processing microcode after the currently executing instruction is completed. the cpu references the ise bit of the icr of the interrupt controller at the beginning of the interrupt processing microcode, checks that the ise bit is 0 (interrupt), and activates the interrupt processing body. the interrupt processing body saves 12 bytes (ps, pc, pcb, dtb, adb, dpr, and a) to the memory area indicated by ssb and ssp, fetches three bytes of interrupt vector and loads them onto pc and pcb, 7.4 hardware interrupt MB90580 series chapter 7: interrupt 85 updates the ilm of ps to a level value of the received interrupt, sets the s flag, then performs branch processing. as a result, the interrupt processing program defined by the user is executed next. figure 7.4.3a illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program. figure 7.4.3b is a diagram of the hardware interrupt operation flow. figure 7.4.3a occurrence and release of hardware interrupt ? an interrupt cause occurs in a peripheral. - the interrupt enable bit in the peripheral is referenced. if interrupts are enabled, the peripheral issues an interrupt request to the interrupt controller. ? upon reception of the interrupt request, the interrupt controller determines the priority levels of simul- taneously requested interrupts. then, the interrupt controller transfers the interrupt level of the corre- sponding interrupt to the cpu. the cpu compares the interrupt level requested by the interrupt controller with the ilm bit of the proc- essor status register. if the comparison shows that the requested level is higher than the current interrupt processing level, the i flag value of the same processor status register is checked. if the check in step shows that the i flag indicates interrupt enable status, the requested level is written to the ilm bit. interrupt processing is performed as soon as the currently executing instruction is completed, then control is transferred to the interrupt processing routine. 2 when the interrupt cause of step ? is cleared by software in the user interrupt processing routine, the interrupt request is completed. ?c a ? ? ? ? ir ps iilm and f 2 m c - 1 6 l c p u f 2 mc-16lx bus register file microcode check comparator peripheral enable ff cause ff level comparator interrupt level il interrupt ps : processor status i : interrupt enable flag ilm : interrupt level mask register ir : instruction register controller 7.4 hardware interrupt 86 chapter 7: interrupt MB90580 series the time required for the cpu to execute the interrupt processing in steps and 2 is shown below. interrupt start : 24 + 6 x table 7.4.3a machine cycles interrupt return : 15 + 6 x table 7.4.3a machine cycles (reti instruction) figure 7.4.3b hardware interrupt operation flow table 7.4.3a compensation values for interrupt processing cycle count address indicated by the stack pointer cycle count compensation value external area, 8-bit data bus +4 external area, even-numbered address +1 external area, odd-numbered address +4 internal area, even-numbered address 0 internal area, odd-numbered address +2 ise = 1 i & if & ie =1 and ilm > il yes no no yes yes no no yes i : flag in ccr ilm : cpu level register if : internal resource interrupt request ie : internal resource interrupt enable flag ise : ei2os enable flag il : internal resource interrupt request level s : flag in ccr int instruction? executing ordinary instruction string instruction updating pc extended intelligent i/o saving ps, pc, pcb, dtb, adb, dpr, s ? 1 fetching interrupt vector fetching and decoding next saving ps, pc, pcb, dtb, adb, dpr, service instruction and a to ssp stack, and setting ilm=il and a to ssp stack, and setting i=0 and ilm=il repetition completed? 7.4 hardware interrupt MB90580 series chapter 7: interrupt 87 7.4.4 hardware interrupt ocurrence when internal resource is being accessed when internal i/o area is being asscessed, the cpu will not response to hardware interrupt immediately, there will be one instruction delay. please refer to chapter 2, section 2.1.3 for details. 7.4.5 interrupt inhibit instruction if f 2 mc-16lx is executing interrupt inhibit instructions, the cpu will not response to hardware interrupt request immediately, there will be one instruction delay. please refer to chapter 2, section 2.1.3 for details. 7.4.6 multiple interrupts the f 2 mc-16lx cpu supports multiple interrupts. if an interrupt of a higher level occurs while another interrupt is being processed, control is transferred to the high-level interrupt after the currently executing instruction is completed. after processing of the high-level interrupt is completed, the original interrupt processing is resumed. an interrupt of the same or lower level may be generated while another interrupt is being processed. if this happens, the new interrupt request is suspended until the current interrupt processing is completed, unless the ilm value or i flag is changed by an instruction. the extended intelligent i/o service cannot be activated from multiple sources; while an extended intelligent i/o service is being processed, all other interrupt requests or extended intelligent i/o service requests are suspended. 7.4.7 register saving in stack upon interrupt figure 7.4.7a registers saved in stack 7.4.8 precaution in using hardware interrupt when there is an hardware interrupt, the interrupt request flag should be cleared before leaving the corresponding interrupt routine to avoid malfunction. some of the resources interrupt request flag will be cleared automatically when certain register(s) is(are) read. in this case, please read those registers to clear the interrupt request flag before leaving the interrupt routine. h l msb lsb ah al pc ps adb pcb dpb dpr register saving upon interrupt word (16 bits) ssp (ssp value before interrupt) ssp (ssp value after interrupt) 7.5 software interrupt 88 chapter 7: interrupt MB90580 series 7.5 software interrupt 7.5.1 overview in response to execution of a special instruction, control is transferred from the program currently executed by the cpu to the interrupt processing program defined by the user. this is called the software interrupt function. a software interrupt occurs always when the software interrupt instruction is executed. the cpu performs the following processing when a software interrupt occurs: saves the values in the pc, ps, ah, al, pcb, dtb, adb, and dpr registers of the cpu to the system stack. sets i in the ps register. interrupts are automatically disabled. fetches the corresponding interrupt vector value, then branches to the processing indicated by that value. a software interrupt request issued by the int instruction has no interrupt request or enable flag. a software interrupt request is always issued by executing the int instruction. the int instruction does not have an interrupt level. therefore, the int instruction does not update ilm. the int instruction clears the i flag to suspend subsequent interrupt requests. 7.5.2 structure software interrupts are handled within the cpu: cpu ........................... microcode: interrupt processing step as shown in table 7.3a, software interrupts share the same interrupt vector area with hardware interrupts. for example, interrupt request number int 13 is used for external interrupt #0 of a hardware interrupt as well as for int #13 of a software interrupt. therefore, external interrupt #0 and int #13 call the same inter- rupt processing routine. 7.5 software interrupt MB90580 series chapter 7: interrupt 89 7.5.3 operation when the cpu fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. the software interrupt processing microcode saves 12 bytes (ps, pc, pcb, dtb, adb, dpr, and a) to the memory area indicated by ssb and ssp. the microcode then fetches three bytes of interrupt vector and loads them onto pc and pcb, resets the i flag, and sets the s flag. then, the microcode performs branch processing. as a result, the interrupt processing program defined by the user application program is executed next. figure 7.5.3a illustrates the flow from the occurrence of a software interrupt until there is no interrupt request in the interrupt processing program. figure 7.5.3a occurrence and release of software interrupt ? the software interrupt instruction is executed. - special cpu registers in the register file are saved according to the microcode corresponding to the software interrupt instruction. ? the interrupt processing is completed with the reti instruction in the user interrupt processing routine. 7.5.4 others when the program bank register (pcb) is ffh, the callv instruction vector area overlaps the table of the int #vct8 instruction. when designing software, ensure that the callv instruction does not use the same address as that of the #vct8 instruction. ram ir ps i s f 2 m c - 1 6 l c p u ps : processor status i : interrupt enable flag ilm : interrupt level mask register ir : instruction register b unit: bus interface unit f 2 mc-16 bus save register file microcode queue fetch instruction bus b unit 7.6 extended intelligent i/o service (ei2os) 90 chapter 7: interrupt MB90580 series 7.6 extended intelligent i/o service (ei 2 os) 7.6.1 overview ei 2 os is a type of hardware interrupt operation that automatically transfers data between i/o and memory. conventionally, data is transferred between i/o and memory by an interrupt processing program. ei 2 os, however, enables data to be transferred as if in dma mode. ei 2 os has the following advantages over the conventional interrupt processing method: writing a transfer program is unnecessary, thus the entire program size can be small. no internal register is used for transfer. therefore, saving the register values is unnecessary, resulting in a higher transfer speed. i/o can stop transfer at any time. therefore, unnecessary data is not transferred. the buffer address can be incremented, decremented, or left unupdated. the i/o address can be incremented, decremented, or left unupdated (when the buffer address is updated). at the end of ei 2 os processing, the cpu automatically branches to the interrupt processing routine after setting the end condition. therefore, the user can identify the end condition type. figure 7.6.1a outlines the ei 2 os. figure 7.6.1a outline of extended intelligent i/o service note: notes:the area that can be specified by ioa is between 000000 h and 00ffff h . the area that can be specified by bap is between 000000 h and ffffff h . the maximum transfer count that can be specified by dct is 65,536. by by bap by ioa isd by ics cpu memory space i/o register buffer peripheral interrupt request interrupt control register interrupt controller i/o register a a ? ? i/o requests transfer. - the interrupt controller selects the descriptor. ? the transfer source and destination are read from the descriptor. data is transferred between i/o and memory. dct 7.6 extended intelligent i/o service (ei2os) MB90580 series chapter 7: interrupt 91 7.6.2 structure ei 2 os is handled by the following four sections: internal resources .................. interrupt enable and request bits: used to control interrupt requests from resources. interrupt controller icr:assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the ei 2 os operation. cpu ....................................... i and ilm:used to compare the requested and current interrupt levels and to identify the interrupt enable status. microcode:e 2 os processing step ram ....................................... descriptor:describes the ei 2 os transfer information. each register is described below. (1) interrupt control register (icr) the interrupt control register is in the interrupt controller. this register corresponds to i/os that have the interrupt function. this register has the following three functions: sets the interrupt level of the corresponding peripheral. selects whether to handle the interrupt of the corresponding peripheral as an ordinary interrupt or as an extended intelligent i/o service. selects the extended intelligent i/o service channel. do not access this register by a read-modify-write instruction, as doing so causes misoperation. interrupt control register (icr) note: ics3 to ics0 are valid only when ei 2 os is activated. set ise to '1' to activate ei 2 os, and to '0' not to activate it. when ei2os is not to be activated, any value can be written to ics3 to ics0. * '1' is always read. ics1 and ics0 are valid for write only. s1 and s0 are valid for read only. ics3 ics2 ics1 ics0 ise il2 il1 il0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 when written address : b0 h Cbf h (w) (w) (w) (w) (w) (w) (w) (w) (0) (0) (0) (0) 0) (1) (1) (1) read/write initial value bit number s1 s0 ise il2 il1 il0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 when read address : b0 h Cbf h (C) (C) (r) (r) (r) (r) (r) (r) (x) (x) (0) (0) 0) (1) (1) (1) read/write initial value bit number 7.6 extended intelligent i/o service (ei2os) 92 chapter 7: interrupt MB90580 series [bits 15 to 12] or [bits 7 to 4] ics3 to ics0 these bits are used to select the ei 2 os channel. these bits are write-only. the value specified in these bits determines the address of the extended intelligent i/o service descriptor in memory, which is explained later. ics is initialized upon a reset. table 7.6.2a shows the correspondence between ics, channel numbers, and descriptor addresses. [bits 13 and 12] or [bits 5 and 4] s0 and s1 these are ei 2 os end status bits. these bits are read-only. when the ei 2 os is completed, the end condition can be identified by checking the value in these bits. these bits are set to '00' upon a reset. table 7.6.2b shows the relationship between the s bits and end conditions . table 7.6.2a ics bits, channel numbers, and descriptor addresses ics3 ics2 ics1 ics0 selected channel descriptor address 0000 0 000100 h 0001 1 000108 h 0010 2 000110 h 0011 3 000118 h 0100 4 000120 h 0101 5 000128 h 0110 6 000130 h 0111 7 000138 h 1000 8 000140 h 1001 9 000148 h 1010 10 000150 h 1011 11 000158 h 1100 12 000160 h 1101 13 000168 h 1110 14 000170 h 1111 15 000178 h table 7.6.2b s bits and end conditions s1 s0 end condition 00 reserved 01 count completion 10 reserved 11 resource request 7.6 extended intelligent i/o service (ei2os) MB90580 series chapter 7: interrupt 93 [bit 11] or [bit 3] ise this is the ei 2 os enable bit. this bit can be read or written to. upon issuance of an interrupt request, ei 2 os is activated if this bit is set to '1' and the interrupt sequence is activated if this bit is set to '0.' if the ei 2 os end condition is satisfied (the s1 and s0 bits are not '00'), the ise bit is cleared to '0.' if the corresponding peripheral does not have the ei 2 os function, the software must set ise to '0.' this bit is initialized to '0' upon a reset. [bits 10 to 8] or [bits 2 to 0] il0, il1, and il2 these are interrupt level setting bits. specify the interrupt level of the corresponding internal resource. these bits can be read and written to. these bits are initialized to level 7 (no interrupt) upon a reset. table 7.6.2c describes the relationship between the interrupt level setting bits and interrupt levels. table 7.6.2c interrupt level setting bits and interrupt levels il2 il1 il0 level 000 0 (highest interrupt level) 001 1 010 2 011 3 100 4 101 5 110 6 (lowest interrupt level) 111 7 (no interrupt) 7.6 extended intelligent i/o service (ei2os) 94 chapter 7: interrupt MB90580 series (2)extended intelligent i/o service descriptor (isd) the extended intelligent i/o service descriptor exists between 000100 h and 00017f h in internal ram, and consists of the following items: data transfer control data status data buffer address pointer figure 7.6.2a shows the configuration of the extended intelligent i/o service descriptor. figure 7.6.2a extended intelligent i/o service descriptor configuration n data counter (dct) this is a 16-bit register that works as a counter corresponding to the number of data items transferred. this counter is decremented by one before data transfer. ei 2 os is terminated when this counter reaches 0. high-order 8 bits of data counter (dcth) low-order 8 bits of data counter (dctl) high-order 8 bits of i/o address pointer (ioah) low-order 8 bits of i/o address pointer (ioal) i 2 os status (iscs) high-order 8 bits of buffer address pointer (baph) medium-order 8 bits of buffer address pointer (bapm) low-order 8 bits of buffer address pointer (bapl) isd start address 000100 h + 8 ics h l b15 b14 b13 b12 b11 b10 b09 b08 15 14 13 12 11 10 9 8 dcth (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number upper byte of data counter b07 b06 b05 b04 b03 b02 b01 b00 76543210 dctl (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number lower byte of data counter 7.6 extended intelligent i/o service (ei2os) MB90580 series chapter 7: interrupt 95 n i/o register address pointer (ioa) this is a 16-bit register that indicates the low-order address (a15 to a0) of the buffer and i/o register used for data transfer to and from the buffer. the high-order address (a23 to a16) are all zeroes, and any i/o between addresses 000000 h and 00ffff h can be specified. n ei 2 os status register (iscs) this eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the i/o register address pointer. this register also indicates whether the buffer address pointer or i/o register address pointer is updated or fixed. * always write 0 to bits 7 to 5 of iscs. each bit is described below. [bit 4] if : specify whether the i/o register address pointer is updated or fixed. note: only increment is allowed. [bit 3] bw: specify the transfer data length. [bit 2] bf: specify whether the buffer address pointer is updated or fixed. note: only the low-order 16 bits of the buffer address are updated. only increment is allowed. 0 the i/o register address pointer is updated after data transfer. 1 the i/o register address pointer is not updated after data transfer . 0 byte 1 word 0 the buffer address pointer is updated after data transfer. 1 the buffer address pointer is not updated after data transfer. a15 a14 a13 a12 a11 a10 a09 a08 15 14 13 12 11 10 9 8 ioah (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number upper address pointer a07 a06 a05 a04 a03 a02 a01 a00 76543210 ioal (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number lower address pointer ifbwbfdirse 76543210 (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 7.6 extended intelligent i/o service (ei2os) 96 chapter 7: interrupt MB90580 series [bit 1] dir: specify the data transfer direction. [bit 0] se: control the termination of the extended intelligent i/o service based on resource requests. n buffer address pointer (bap) this 24-bit register holds the address used for the next ei 2 os transfer. bap exists for each ei 2 os chan- nel. therefore, each ei 2 os channel can be used for transfer with anywhere in the 16-mbyte space. note: if the bf bit of iscs is set to '0' (update enabled), only the low-order 16 bits of bap changes and baph does not change. 0 i/o ? buffer 1 buffer ? i/o 0 the extended intelligent i/o service is not terminated by a resource request. 1 the extended intelligent i/o service is terminated by a resource request. 7.6 extended intelligent i/o service (ei2os) MB90580 series chapter 7: interrupt 97 7.6.3 operation . figure 7.6.3a ei 2 os operation flow ise = 1 dir = 1 bf = 0 se = 1 dct = 00 if = 0 no yes no yes no yes no yes no yes yes no bap : buffer address pointer i/oa : i/o address pointer isd : ei 2 os descriptor iscs : ei 2 os status dct : data counter ise : ei 2 os enable bit s1 and s0 : ei 2 os end status interrupt request issued reading isd/iscs interrupt sequence end request from resource data indicated by ioa (data transfer) memory indicated by bap data indicated by bap (data transfer) memory indicated by ioa update value updating ioa updating bap decrementing dct setting s1 and s0 to '00' clearing resource cpu operation return setting s1 and s0 to '01' setting s1 and s0 to '11' clearing ise to '0' interrupt sequence from internal resource ? ? depends on bw. update value depends on bw. interrupt request 7.6 extended intelligent i/o service (ei2os) 98 chapter 7: interrupt MB90580 series figure 7.6.3b ei 2 os use flow processing by ei2os processing by cpu i 2 os initialization job execution (interrupt request) normal termination data transfer re-setting of extended intelligent i/o service (switching channels) processing data in buffer and (ise = 1) 7.6 extended intelligent i/o service (ei2os) MB90580 series chapter 7: interrupt 99 7.6.4 ei 2 os execution time (1) when data transfer continues (when the stop condition is not satisfied) ei2os execution time = (value in table 7.6.4a + value in table 7.6.4b) machine cycle (2) when a stop request is issued from a resource ei2os execution time = (36 + 6 value of table 7.4.3a) machine cycles (3) when the counting is completed ei2os execution time = (value of table 7.6.4a + value of table 7.6.4b + (21 + 6 value of table 7.4.3a) machine cycles b : byte data transfer 8 : 8-bit external bus word transfer e : even address word transfer o : odd address word transfer table 7.6.4a execution time when the extended i2os continues iscs se bit set to '0' set to '1' i/o address pointer fixed updated fixed updated buffer address pointer fixed 32 34 33 35 updated 34 36 35 37 table 7.6.4b data transfer compensation values for extended i2os execution time i/o address pointer internal access external access b/e o b/e 8/o buffer address pointer internal access b/e 0 +2 +1 +4 o +2+4+3+6 external access b/e+1+3+2+5 8/o+4+6+5+8 7.7 exceptions 100 chapter 7: interrupt MB90580 series 7.7 exceptions the f 2 mc-16lx performs exception processing when the following event occurs: ? execution of an undefined instruction exception processing is fundamentally the same as interrupt processing. when an exception is detected between instructions, exception processing is performed separately from ordinary processing. in general, exception processing is performed as a result of an unexpected operation. fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. 7.7.1 exception due to execution of an undefined instruction the f 2 mc-16lx handles all codes that are not defined in the instruction map as undefined instructions. when an undefined instruction is executed, processing equivalent to the int 10 software interrupt instruction is performed. specifically, the al, ah, dpr, dtb, adb, pcb, pc, and ps values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. in addition, the i flag is cleared and the s flag is set. the pc value saved in the stack is the address at which the undefined instruction is stored. processing can be restored by the reti instruction, but is of no use, however, because the same exception occurs again. chapter 8: parallel ports 8.1 outline in MB90580 series, there are 10 parallel ports which are as follows: ? port 0 (8 cmos i/o pins) ? port 1 (8 cmos i/o pins) ? port 2 (8 cmos i/o pins) ? port 3 (8 cmos i/o pins) ? port 4 (8 cmos i/o pins with open-drain control) ? port 5 (8 cmos i/o pins) ? port 6 (6 cmos i/o pins) ? port 7 (4 cmos i/o pins) ? port 8 (8 cmos i/o pins) ? port 9 (8 cmos i/o pins) ? port a (3 cmos i/o pins) each pin of the ports can be specified as input or output using the direction register if the corresponding peripheral does not use the pin. when a pin is specified as input, the value of the pin level is read from a data register. when a pin is specified as output, the data register latch value is read from the data register. the above also applies to a read operation for a read-modify-write instruction. when a data register is read while the corresponding port is used as a control output, control output value is read from the data register regardless of the direction register value. when an input pin is changed into an output pin, care must be taken to use a read-modify-write instruction (such as a bit set instruction) to set output data in the data register beforehand. in this case, the data input from the pin is read instead of the data register latch value. 8.2 block diagram 102 chapter 8: parallel ports MB90580 series 8.2 block diagram figure 8.2a block diagram of i/o port figure 8.2b block diagram of input resistor register figure 8.2c block diagram of output pin register internal data bus data register read data register write direction register write direction register read data register direction register pin data register direction register resistor register pull-up resistor (about 50 k w ) pin internal data bus data register direction register pin register pin internal data bus 8.3 registers and register details MB90580 series chapter 8: parallel ports 103 8.3 registers and register details figure 8.3a registers of parallel ports p07 p06 p05 p04 p03 p02 p01 p00 p17 p27 p37 p47 p57 p87 p97 p26 p36 p46 p56 p15 p25 p35 p45 p55 p65 p14 p24 p34 p44 p54 p64 p13 p23 p33 p43 p53 p63 p12 p22 p32 p42 p52 p62 p11 p21 p31 p41 p51 p61 p10 p20 p30 p40 p50 p60 p86 p96 p85 p95 p84 p94 p83 p93 p82 p92 p81 p91 p80 p90 p74 p73 p72 p71 pa2 pa1 pa0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 p17 address : 000000 h address : 000001 h address : 000002 h address : 000003 h address : 000004 h address : 000005 h address : 000006 h address : 000007 h address : 000008 h address : 000009 h address : 00000a h bit port 0 data register (pdr0) port 1 data register (pdr1) port 2 data register (pdr2) port 3 data register (pdr3) port 4 data register (pdr4) port 5 data register (pdr5) port 6 data register (pdr6) port 7 data register (pdr7) port 8 data register (pdr8) port 9 data register (pdr9) port a data register (pdra) d07 d06 d05 d04 d03 d02 d01 d00 d17 d27 d37 d47 d57 d87 d97 d26 d36 d46 d56 d15 d25 d35 d45 d55 d65 d14 d24 d34 d44 d54 d64 d13 d23 d33 d43 d53 d63 d12 d22 d32 d42 d52 d62 d11 d21 d31 d41 d51 d61 d10 d20 d30 d40 d50 d60 d86 d96 d85 d95 d84 d94 d83 d93 d82 d92 d81 d91 d80 d90 d74 d73 d72 d71 da2 da1 da0 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 d17 address : 000010 h address : 000011 h address : 000012 h address : 000013 h address : 000014 h address : 000015 h address : 000016 h address : 000017 h address : 000018 h address : 000019 h address : 00001a h bit port 0 data register (ddr0) port 1 data register (ddr1) port 2 data register (ddr2) port 3 data register (ddr3) port 4 data register (ddr4) port 5 data register (ddr5) port 6 data register (ddr6) port 7 data register (ddr7) port 8 data register (ddr8) port 9 data register (ddr9) port a data register (ddra) 15 14 13 12 11 10 9 8 address : 00001b h od47 od46 od45 od44 od43 od42 od41 od40 address : 00001c h bit 76 5432 10 bit ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 port 4 pin register (odr4) port 5 analog input enable register (ader) address : 00008c h address : 00008d h address : 00008e h 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 bit rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 rd65 rd64 rd63 rd62 rd61 rd60 port 0 resistor register (rdr0) port 1 resistor register (rdr1) port 6 resistor register (rdr6) 15 14 13 12 11 10 9 8 address : 0000a3 h address : 0000a2 h bit 76 5432 10 bit ln7 ln6 ln5 ln4 ln3 ln2 ln1 ln0 low noise output select register (upper) (lnsrh) low noise output select register (lower) (lnsrl) ln8 ln9 lna lnb 8.3 registers and register details 104 chapter 8: parallel ports MB90580 series 8.3.1 port data register note: note that r/w for i/o ports differ from r/w for memory in the following points: m input mode read: the level of the corresponding pin is read. write: data is written to an output latch. m output mode read: the data register latch value is read. write: the data is output to the corresponding pin. p07 p06 p05 p04 p03 p02 p01 p00 p17 p16 p15 p14 p13 p12 p11 p10 p27 p26 p25 p24 p23 p22 p21 p20 p37 p36 p35 p34 p33 p32 p31 p30 p47 p46 p45 p44 p43 p42 p41 p40 p57 p56 p55 p54 p53 p52 p51 p50 p65 p64 p63 p62 p61 p60 p74 p73 p72 p71 p87 p86 p85 p84 p83 p82 p81 p80 p97 p96 p95 p94 p93 p92 p91 p90 pa2 pa1 pa0 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 pdr0 address: 000000 h pdr1 address: 000001 h pdr2 address: 000002 h pdr3 address: 000003 h pdr4 address: 000004 h pdr5 address: 000005 h pdr6 address: 000006 h pdr7 address: 000007 h pdr8 address: 000008 h pdr9 address: 000009 h pdra address: 00000a h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value access xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx --xxxxxx ---xxxx- xxxxxxxx xxxxxxxx -----xxx 8.3 registers and register details MB90580 series chapter 8: parallel ports 105 8.3.2 port direction registers when a pin is used as a port, the corresponding pin is controlled as described below: 0 input mode [initial value] 1 output mode d07 d06 d05 d04 d03 d02 d01 d00 d17 d16 d15 d14 d13 d12 d11 d10 d27 d26 d25 d24 d23 d22 d21 d20 d37 d36 d35 d34 d33 d32 d31 d30 d47 d46 d45 d44 d43 d42 d41 d40 d57 d56 d55 d54 d53 d52 d51 d50 d65 d64 d63 d62 d61 d60 d74 d73 d72 d71 d87 d86 d85 d84 d83 d82 d81 d80 d97 d96 d95 d94 d93 d92 d91 d90 da2 da1 da0 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 15 14 13 12 11 10 9 8 7 654 3 2 1 0 ddr0 address: 000010 h ddr1 address: 000011 h ddr2 address: 000012 h ddr3 address: 000013 h ddr4 address: 000014 h ddr5 address: 000015 h ddr6 address: 000016 h ddr7 address: 000017 h ddr8 address: 000018 h ddr9 address: 000019 h ddra address: 00001a h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b 00000000 b --000000 b - - - 0000- b 00000000 b 00000000 b - - - - -000 b initial value access 8.3 registers and register details 106 chapter 8: parallel ports MB90580 series 8.3.3 output pin register this register controls the open drain in output mode. note: this register is not used in input mode. (output hi-z) note: input or output mode is determined by the direction register (ddr). note: no pull-up resistor is used during hardware standby and stop (spl=1). (high imped- ance) note: this function is inhibited when an external bus is used. when using an external bus, do not write data in this register. 8.3.4 input resistor register this register controls whether to use a pull-up resistor in input mode. note: this register has no use in output mode (no pull-up resistor is used). note: input or output mode is determined by the direction register (ddr). note: no pull-up resistor is used during hardware standby and stop (spl=1). (high impedance) note: this function is inhibited when an external bus is used. when using an external bus, do not write data in this register. 0 standard output port in output mode [initial value] 1 open drain output port in output mode 0 no pull-up resistor used in input mode. [initial value] 1 pull-up resistor used in input mode. od47 od46 od45 od44 od43 od42 od41 od40 15 14 13 12 11 10 9 8 address : 00001b h port 4 pin register r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 read/write initial value bit number odr4 rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 15 16 15 14 13 12 11 10 address : 00008d h rd07 rd06 rd65 rd64 rd63 rd62 rd61 rd60 76543 210 address : 00008e h rd05 rd04 rd03 rd02 rd01 rd00 76543 210 address : 00008c h port 6 resistor register port 0 resistor register port 1 resistor register r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 read/write initial value r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 read/write initial value r/w r/w r/w r/w r/w r/w r/w r/w - - 0 0 0 0 0 0 read/write initial value bit number bit number bit number rdr6 rdr1 rdr0 8.3 registers and register details MB90580 series chapter 8: parallel ports 107 8.3.5 analogue input enable register this register controls the .behaviour of port 5. note: when an intermediate voltage level is applied to the pin during port input mode, a leakage current will be induced. in this case, configure the pin to analogue input mode instead. 8.3.6 low noise output select register these two register are used to select the low noise output buffer for port 0 to port a and the tx output of ie bus. [bit 15 - 12] - unused bits [bit 11] - lnb controls tx pin of ie bus [bit 10] - lna controls port a 0 port input mode 1 analogue input mode [initial value] 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 76543 210 address : 00001c h bit number port 5 analogue enable register ader r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 read/write initial value 15 14 13 12 11 10 9 8 address : 0000a3 h address : 0000a2 h 76 5432 10 ln7 ln6 ln5 ln4 ln3 ln2 ln1 ln0 low noise output select register (upper) low noise output select register (lower) ln8 ln9 lna lnb r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 read/write initial value read/write initial value 0 0 0 0 bit number bit number lnsrl lnsrh 8.3 registers and register details 108 chapter 8: parallel ports MB90580 series [bit 9] - ln9 controls port 9 [bit 8] - ln8 controls port 8 [bit 7] - ln7 controls port 7 [bit 6] - ln6 controls port 6 [bit 5] - ln5 controls port 5 [bit 4] - ln4 controls port 4 [bit 3] - ln3 controls port 3 [bit 2] - ln2 controls port 2 [bit 1] - ln1 controls port 1 [bit 0] - ln0 control port 0 note: these two register are not available for mb90v580. note: when low noise output buffer is selected, the driving power will be decreased. 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer 0 normal output buffer [initial value] 1 low noise output buffer chapter 9: dtp/external interrupt 9.1 outline the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16lx cpu. the dtp receives dma and interrupt processing requests from external peripherals and passes requests to the f 2 mc-16lx cpu to activate the extended intelligent i/o service (ei 2 os) or interrupt processing. two request levels ("h" and "l") are provideed for the extended intelligent i/o service (ei 2 os). for external interrupt requests, generating interrupts on a rising edge or falling edge as well as "h" and "l" level can be selected, giving a total of four types. 9.2 block diagram figure 9.2a block diagram of dtp/external interrupt 4 4 4 8 4 interrupt/dtp enable register gate cause f/f edge detection circuit request input interrupt/dtp cause register request level setting register f 2 mc-16lx bus 9.3 registers and register details 110 chapter 9: dtp/external interrupt MB90580 series 9.3 registers and register details 9.3.1 interrupt/dtp enable register (enir: enable interrupt request register) enir enables the function to issue a request to the interrupt controller using a device pin as an external interrupt/dtp request input. a pin corresponding to a '1' bit of this register is used as an external interrupt/dtp request input. a pin corresponding to a '0' bit holds the external interrupt/dtp request input cause, but does not issue a request to the interrupt controller. en3 en2 en1 en0 en4 76543 2 10 en5 en7 en6 address : 000030 h 15 14 13 12 11 10 9 8 address : 000031 h er3 er2 er1 er0 er4 er5 er7 er6 interrupt/dtp enable register enir interrupt/dtp cause register eirr (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write address : 000033 h la2 76543 2 10 address : 000032 h 15 14 13 12 11 10 9 8 lb1 la1 lb0 la0 lb2 lb3 la3 la6 lb5 la5 lb4 la4 lb6 lb7 la7 request level setting register (lower byte) elvr (low) request level setting register (higher byte) elvr (high) bit number bit number (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write en3 en2 en1 en0 en4 76543 2 10 en5 en7 en6 address : 000030 h interrupt/dtp enable register enir (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 9.3 registers and register details MB90580 series chapter 9: dtp/external interrupt 111 9.3.2 interrupt/dtp cause register (eirr: external interrupt request register) when read, eirr indicates the current external interrupt/dtp requests. when written, eirr clears the flip-flop values indicating those requests. external interrupt/dtp requests exist at the pins corresponding to the '1' bits of this register. writing '0' to a bit of this register clears the corresponding request flip-flop value. writing '1' performs no operation. '1' is always read from this register by a read-modify-write instruction. 9.3.3 request level setting register (elvr: external level register) elvr is used to select a request detection factor. each pin is assigned two bits as described in the table below. if a request is to be detected based on a level, the register value is maintained while the input is active even when it is cleared. lbx lax interrupt request detection factor 0 0 1 1 0 1 0 1 l level pin input h level pin input rising edge pin input falling edge pin input 15 14 13 12 11 10 9 8 address : 000031 h er3 er2 er1 er0 er4 er5 er7 er6 interrupt/dtp cause register eirr bit number (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write address : 000033 h la2 76543 2 10 address : 000032 h 15 14 13 12 11 10 9 8 lb1 la1 lb0 la0 lb2 lb3 la3 la6 lb5 la5 lb4 la4 lb6 lb7 la7 request level setting register (lower byte) elvr (low) request level setting register (higher byte) elvr (high) bit number bit number (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 9.4 operations 112 chapter 9: dtp/external interrupt MB90580 series 9.4 operations 9.4.1 external interrupts once an external interrupt request is set, this resource issues an interrupt request signal to the interrupt controller when a request specified by the elvr register is input to the corresponding pin. the interrupt controller identifies the priority levels of the simultaneous interrupts, and issues an interrupt request to the f 2 mc-16 cpu if the interrupt from this resource has the highest priority level. the f 2 mc-16 cpu compares the ilm bit of its internal ccr register and the interrupt request. if the interrupt level of the request is higher than that indicated by the ilm bit, the f 2 mc-16 cpu activates the hardware interrupt pro- cessing microprogram as soon as the currently executing instruction is terminated. figure 9.4.1a external interrupt in the hardware interrupt processing microprogram, the cpu reads the ise bit information from the interrupt controller, identifies that the request is for interrupt processing based on that information, and branches to the interrupt processing microprogram. the interrupt processing microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. then, the microprogram transfers the jump destination address of the macro instruction generated from the vector to the program counter, and executes the user interrupt processing program. elvr eirr enir icr xx icr yy cmp ilm il nta cmp f 2 mc-16cpu external interrupt/dtp other request interrupt controller cause 9.4 operations MB90580 series chapter 9: dtp/external interrupt 113 9.4.2 dtp operation to activate the intelligent i/o service, the user program initially sets the address of a register, assigned between 000000 h and 0000ff h , in the i/o address pointer of the intelligent i/o service descriptor. then, the user program sets the start address of the memory buffer in the buffer address pointer. the dtp operation sequence is almost the same as for external interrupts. the operation is identical until the cpu activates the hardware interrupt processing microprogram. then, for the dtp, control is transferred to the intelligent i/o service processing microprogram, since the ise bit read by the cpu within the hardware interrupt processing microprogram indicates the dtp. once the intelligent i/o service is activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between the peripheral and the chip. the external peripheral must cancel the interrupt request to this chip within three machine cycles after the transfer is made. when the transfer is completed, the descriptor is updated, and the interrupt controller generates a signal that clears the transfer cause. upon receiving the signal to clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request from the pin. for details of the intelligent i/o service processing, refer to the mb90700 programming manual. figure 9.4.2a timing to cancel the external interrupt at the end of dtp operation figure 9.4.2b sample interface to the external peripheral interrupt cause internal operation address bus pin data bus pin read signal write signal selecting and reading descriptor edge request or h level request * when data is transferred from the i/o register to memory read address write address read data write data cancel within three machine cycles. in the intelligent i/o service data, address dtp core memory MB90580 int irq external peripheral register internal bus cancel within three machine cycles after transfer. bus 9.4 operations 114 chapter 9: dtp/external interrupt MB90580 series 9.4.3 switching between external interrupt and dtp requests to switch between external interrupt and dtp requests, use the ise bit in the icr register corresponding to this resource, which is in the interrupt controller. each pin is individually assigned icr. thus, a pin is used for a dtp request if '1' is written to the ise bit of the corresponding icr, and is used for an external interrupt request if '0' is written to the bit. figure 9.4.3a switching between external interrupt and dtp requests dtp icr xx icr yy 1 0 f2mc-16 cpu pin external external interrupt interrupt/dtp interrupt controller 9.5 notes on use MB90580 series chapter 9: dtp/external interrupt 115 9.5 notes on use 9.5.1 conditions on the externally connected peripheral when dtp is used dtp supports only external peripherals that automatically clear a request once a transfer is completed. the system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts. otherwise, this resource assumes that a transfer request is issued. 9.5.2 recovery from standby to use an external interrupt to recover from the standby state in clock stop mode, use an h level request as an input request. a l level request may result in misoperation. if an edge request is used, recovery from the standby state in clock stop mode cannot be performed. 9.5.3 external interrupt/dtp operation procedure to set registers in the external interrupt/dtp, follow the steps below: 1. disable the bits corresponding to the enable register. 2. set the bits corresponding to the request level setting register. 3. clear the bits corresponding to the cause register. 4. enable the bits corresponding to the enable register. (steps 3. and 4. can be simultaneously performed by word specification.) to set a register in this resource, ensure that the enable register is disabled. before enabling the enable register, ensure that the cause register is cleared. clearing the cause register prevents a false interrupt cause from being determined while registers are set or interrupts are enabled. 9.5.4 external interrupt request level ? to detect an edge for a edge request level, the pulse width must be at least three machine cycles. - if the request input level is related to level setting, the request to the interrupt controller is kept active. because of the internal hold circuit, the request is kept active even if it is input from the external device and then canceled. to cancel the request to the interrupt controller, clear the cause hold circuit. figure 9.5.4a clearing the cause hold circuit upon level set figure 9.5.4b interrupt cause and interrupt request to the interrupt controller while interrupts are enabled interrupt cause level detection cause f/f (cause hold circuit) the cause is kept held unless cleared. enable gate to interrupt controller interrupt cause interrupt request to h level set inactive when the cause f/f is cleared. the interrupt controller chapter 10: delayed interrupt generation module 10.1 outline the delayed interrupt generation module generates interrupts for switching tasks for development on a real-time operating system (realos series). the module can be used to generate softwarewise generates hardware interrupt requests to the cpu and cancel the interrupts. this module does not conform to the extended intelligent i/o service (ei 2 os). 10.2 block diagram figure 10.2a block diagram of delayed interrupt generation module 10.3 registers and register details delayed interrupt cause issuance/cancellation register (dirr: delayed interrupt request register) dirr controls issuance and cancellation of delayed interrupt requests. writing '1' to this register issues a delayed interrupt request, and writing '0' cancels the delayed interrupt request. upon a reset, the request is canceled. either '0' or '1' can be written to the reserved bit area. to access this register, use the set bit or clear bit instruction for future expansions. f 2 mc-16lx bus delayed interrupt cause issuance/cancellation decoder cause latch r0 76543 2 10 address : 00009f h delayed interrupt cause issuance/cancellation register dirr (C) (C) (C) (C) (C) (C) (C) (0) initial value bit number (C) (C) (C) (C) (C) (C) (C) (r/w) read/write 10.4 operations 118 chapter 10: delayed interrupt generation module MB90580 series 10.4 operations 10.4.1 delayed interrupt occurrence when the cpu writes '1' to the relevant bit of dirr by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. if this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the f 2 mc-16 cpu. the f 2 mc-16 cpu compares the ilm bit of its internal ccr register and the interrupt request, and starts the hardware interrupt processing microprogram as soon as the current instruction is completed if the interrupt level of the request is higher than that of the ilm bit. the interrupt processing routine for this interrupt is thus executed. figure 10.4.1a delayed interrupt issuance the interrupt cause is cleared and tasks are switched by writing '0' to the corresponding bit of ddir in the interrupt processing routine. 10.5 notes on operation 10.5.1 delayed interrupt request lock this lock is set by writing '1' to the corresponding bit of dirr, and is cleared by writing '0' to the same bit. therefore, interrupt processing is reactivated immediately after control returns from interrupt processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt processing routine. ddir icr xx icr yy cmp ilm il nta cmp write delayed interrupt source module interrupt controller other requests f 2 mc-16cpu chapter 11: communication prescaler 11.1 outline the operation clock for the uart is obtained by dividing the machine clock. uart is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler. the clock division control register (cdcr) controls the machine clock division. 11.2 block diagram figure 11.2a block diagram of communication prescaler clock division control register (cdcr) md div3 div2 div1 div0 clock divider programmable to uart from main clock f 2 mc-16lx bus 11.3 register and register details 120 chapter 11: communication prescaler MB90580 series 11.3 register and register details 11.3.1 clock division control registers [bit 15] md (machine clock divide mode select): this bit is used to control the operation of the communication prescaler. [bits 11, 10, 9, and 8] div3 to div0 (divide 3 to 0): these bits are used to determine the machine clock division ratio. note: when the division ratio is changed, allow two cycles for the clock to stabilize before starting communication. note: in actual application, please use the values other than 1111. 0 the communication prescaler is disabled. [initial value] 1 the communication prescaler is enabled. div3 div2 div1 div0 division ratio 1111reserved [initial value] 1110 2 1101 3 1100 4 1011 5 1010 6 1001 7 1000 8 div3 div2 div1 div0 15 14 13 12 11 10 9 8 md address : 00002c h cdcr0 (0) (C) (C) (C) (1) (1) (1) (1) initial value bit number (r/w) (C) (C) (C) (r/w) (r/w) (r/w) (r/w) read/write clock division control register 0, 1, 2, 3, 4 00002e h 000034 h cdcr1 cdcr2 000087 h 00008f h cdcr3 cdcr4 11.4 operations MB90580 series chapter 11: communication prescaler 121 11.4 operations depending on the machine clock f to be used, the communication prescaler register should be set as follows. for details please refer to chapter 12, uart. . when using the machine clock and the div at a different setting other than those mentioned above, f /div should not exceed 4.25 mhz. machine clock f div div3 div2 div1 div0 f /div 4 mhz 41100 1 mhz 6 mhz 61010 8 mhz 81000 6 mhz 31101 2 mhz 8 mhz 41100 10 mhz 51011 12 mhz 61010 14 mhz 71001 16 mhz 81000 8 mhz 21110 4 mhz 12 mhz 31101 16 mhz 41100 chapter 12: uart 12.1 outline uart is a serial i/o port for asynchronous communications or clk synchronous communications. uart has the following features: ? full-duplex double buffers ? asynchronous or clk synchronous communications ? multi-processor mode ? built-in dedicated baud rate generator ? flexible baud rate setting by external clock ? error detection (parity, framing, and overrun) ? nrz sign transfer signals ? intelligent i/o service asynchronous: 9615, 31250, 4808, 2404, 1202 bps clk synchronous: 1 m, 500 k, 250 k, 125 k, 62.5 kbps (at an internal machine clock of 6, 8, 10, 12, or 16 mhz) 12.2 block diagram 124 chapter 12: uart MB90580 series 12.2 block diagram figure 12.2a block diagram of uart f 2 mc-16lx bus md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sidr0/1/2 sodr0/1/2 sot0/1/2/3/4 sck0/1/2/3/4 sin0/1/2/3/4 baud rate upper part of ppg timer external clock clock reception clock transmission clock reception transmission reception control generator circuit selection (to cpu) interrupt reception bit circuit counter reception parity counter transmission control transmission transmission bit transmission reception status i 2 os reception error reception shifter circuit start circuit counter parity counter judgment circuit signal (to cpu) transmission shifter start of transmission smr0/1/2/3/4 scr0/1/2/3/4 ssr0/1/2/3/4 control signal register register register start bit detect circuit (to cpu) (ppg1) from communication prescaler interrupt end of reception 12.3 register and register details MB90580 series chapter 12: uart 125 12.3 register and register details figure 12.3a registers of uart cs0 reserved scke soe cs1 76543 2 10 cs2 md1 md0 address : 000020 h serial mode register smr0 address : 000023 h serial control register scr0 a/d rec rxe txe cl 15 14 13 12 11 10 9 8 sbl pen address : 000021 h p tdre rie tie rdrf 15 14 13 12 11 10 9 8 fre pe ore serial status register 000024 h 000025 h 000027 h ssr0 000028 h 000029 h 00002b h (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number bit number d3 d2 d1 d0 d4 76543 2 10 d5 d7 d6 address : 000022 h serial input register/serial output register sidr0/sodr0 000026 h sidr1/sodr1 00002a h sidr2/sodr2 bit number smr1 smr2 scr1 scr2 ssr1 ssr2 000082 h 000089 h 00008a h 000088 h 000085 h 000084 h 000083 h 00008b h ssr3 ssr4 sidr3/sodr3 sidr4/sodr4 scr3 scr4 smr3 smr4 (0) (0) (0) (0) (0) (1) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write (0) (0) (0) (0) (1) (-) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 12.3 register and register details 126 chapter 12: uart MB90580 series 12.3.1 serial mode register (smr0/1/2/3/4) the smr register specifies the uart operation mode. set the operation mode while the uart is stopped. do not write data in this register during uart operation. [bits 7 and 6] md1 and md0 (mode select): these bits are used to select the uart operation mode. note: in clk asynchronous multi-processor mode (mode 1), two or more slave cpus are connected to a single host cpu. this resource cannot identify the format of the received data. therefore, this resource only supports a master in multi-processor mode. since the parity check function cannot be used, write '0' to pen of the scr register. [bits 5 to 3] cs2, cs1, and cs0 (clock select):these bits are used to select the baud rate clock source. when a dedicated baud rate generator is selected, the baud rate is determined at the same time. note: if an internal timer is selected, timer 0 is used for uart0 and uart3 in the MB90580 series. note: if an internal timer is selected, timer 1 is used for uart1 and uart4 in the MB90580 series. note: if an internal timer is selected, timer 0 is used for uart2 in the MB90580 series. [bit 2] reserved bit always write '0' to this bit. mode md1 md0 operation mode 0 0 0 asynchronous normal mode 1 0 1 asynchronous multi-processor mode 2 1 0 clk synchronous mode - 1 1 setting inhibited cs2 cs1 cs0 clock input 000 b to 100 b dedicated baud rate generator 101reserved 1 1 0 internal timer 1 1 1 external clock cs0 reserved scke soe cs1 76543 2 10 cs2 md1 md0 address : 000020 h serial mode register smr0 000024 h 000028 h (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write smr1 smr2 000088 h 000082 h smr3 smr4 12.3 register and register details MB90580 series chapter 12: uart 127 [bit 1] scke (sclk enable): this bit is used to specify whether to use the sck0 pin as a clock input pin or clock output pin in clk synchronous mode (mode 2) communication. set '0' in this bit in clk asynchronous mode or external clock mode. note: to use the sck0 pin as a clock input pin, an external clock source must have been selected. [bit 0] soe (serial output enable): this bit is used to specify whether the external pin is used as a serial output pin (sot0) or i/o port pin. 0 the sck0 pin is used as a clock input pin. [initial value] 1 the sck0 pin is used as a clock output pin. 0 the external pin is used as a general-purpose i/o port pin. [initial value] 1 the external pin is used as a serial data output (sot0) pin. 12.3 register and register details 128 chapter 12: uart MB90580 series 12.3.2 serial control register (scr0/1/2/3/4) the scr register controls the transfer protocol for serial communications. [bit 15] pen (parity enable): this bit is used to specify whether to perform serial data communication using a parity bit. note: a parity bit can be added only in normal asynchronous communication mode (mode 0). no parity bit can be added in multi-processor mode (mode 1) or clk synchronous communication mode (mode 2). [bit 14] p (parity): this bit is used to specify an even- or odd-numbered parity for data communications with parity. [bit 13] sbl (stop bit length) this bit is used to specify the length of the stop bit, which is used as a frame end mark in asynchronous communications. [bit 12] cl (character length): this bit is used to specify the data length of each frame to be sent or received. note: 7-bit data can be handled only in normal synchronous communication mode (mode 0). specify 8-bit data in multi-processor mode (mode 1) or clk synchronous communica- tion mode (mode 2). 0 with parity [initial value] 1 without parity 0 even-numbered parity [initial value] 1 odd-numbered parity 0 1 stop bit [initial value] 1 2 stop bits 0 7-bit data [initial value] 1 8-bit data serial control register scr0 a/d rec rxe txe cl 15 14 13 12 11 10 9 8 sbl pen address : 000021 h p 000025 h 000029 h bit number scr1 scr2 000089 h 000083 h scr3 scr4 (0) (0) (0) (0) (0) (1) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 12.3 register and register details MB90580 series chapter 12: uart 129 [bit 11> a/d (address/data): this bit is used to specify the data format of the frame to be sent or received in multi-processor asyn- chronous communication mode (mode 1). [bit 10] rec (receiver error clear): this bit is used to clear the ssr register error flags (pe, ore, and fre). writing '1' to this bit is invalid. '1' is always read from this bit. [bit 9] rxe (receiver enable): this bit is used to control uart reception. note: if reception is disabled while data is being received (being input to the reception shift register), reception is terminated when the reception of that frame is completed and the reception data is stored in the reception data buffer (sidr register). [bit 8] txe (transmitter enable): this bit is used to control uart transmission. note: if transmission is disabled while data is being transmitted (being output from the trans- mission register), transmission is terminated after all data in the transmission data buffer (sodr register) has been output. 0 data frame [initial value] 1 address frame 0 disables reception. [initial value] 1 enables reception. 0 disables transmission [initial value] 1 enables transmission. 12.3 register and register details 130 chapter 12: uart MB90580 series 12.3.3 serial input data register (sidr0/1/2/3/4)/ serial ouput data register (sodr0/1/2/3/4) these registers are data buffer registers for transmission and reception. when a data item is seven bits long, the high-order one bit (d7) is invalid. to write a data item in the sodr register, ensure that '1' is written to tdre of the ssr register. note: writing a data item at this address means to write it to the sodr register. reading this address means to read the sidr register. 12.3.4 serial status register (ssr0/1/2/3/4) the ssr register consists of the flags indicating the uart operation. [bit 15] pe (parity error) this interrupt request flag is set when a parity error occurs during reception. to clear a set flag, write '0' to the rec bit (bit 10) of the scr register. when this bit is set, the data in sidr is invalid. [bit 14] ore (overrun error): this interrupt request flag is set when an overrun error occurs during reception. to clear a set flag, write '0' to the rec bit (bit 10) of the scr register. when this bit is set, the data in sidr is invalid. 0 no parity error has occurred. [initial value] 1 a parity error has occurred. 0 no overrun error has occurred. [initial value] 1 an overrun error has occurred. d3 d2 d1 d0 d4 76543 2 10 d5 d7 d6 address : 000022 h serial input register/serial output register sidr0/sodr0 000026 h sidr1/sodr1 00002a h sidr2/sodr2 bit number 00008a h 000084 h sidr3/sodr3 sidr4/sodr4 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write d3 d2 d1 d0 d4 76543 2 10 d5 d7 d6 address : 000022 h serial input register/serial output register sidr0/sodr0 000026 h sidr1/sodr1 00002a h sidr2/sodr2 bit number 00008a h 000084 h sidr3/sodr3 sidr4/sodr4 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write 12.3 register and register details MB90580 series chapter 12: uart 131 [bit 13] fre (framing error) this interrupt request flag is set when a framing error occurs during reception. to clear a set flag, write '0' to the rec bit (bit 10) of the scr register. when this bit is set, the data in sidr is invalid. [bit 12] rdrf (receiver data register full): this interrupt request flag indicates that the sidr register contains received data. this flag is set when received data is loaded into the sidr register. this flag is automatically cleared when the sidr register is read. [bit 11] tdre (transmitter data register empty): this interrupt request flag indicates that transmission data can be written into the sodr register. this flag is cleared when transmission data is written into the sodr register. then, when the written data is loaded into the transmission shifter and transfer starts, this flag is set again, indicating the next transmission data item can be written. 0: writing transmission data is disabled. 1: writing transmission data is enabled. [bit 9] rie (receiver interrupt enable): this bit is used to control reception interrupts. note: reception interrupt causes include normal reception by rdrf in addition to errors due to pe, ore, and fre. [bit 8] tie (transmitter interrupt enable): this bit is used to control transmission interrupts. note: transmission interrupt causes include transmission requests by tdre. 0 no framing error has occurred. [initial value] 1 a framing error has occurred. 0 no received data exists. [initial value] 1 received data exists. 0 writing transmission data is disabled. 1 writing transmission data is enabled. [initial value] 0 interrupts are disabled [initial value] 1 interrupts are enabled. 0 interrupts are disabled [initial value] 1 interrupts are enabled. 12.4 operations 132 chapter 12: uart MB90580 series 12.4 operations 12.4.1 operation modes table 12.4.1a lists the operation modes of uart. the modes can be switched by setting a value in the smr or scr register. note: in asynchronous mode, the stop bit length can be specified for transmission only; the stop bit is always one bit long for reception. if a two-bit stop bit length is specified, the uart does not operate. note: when using clock synchronous mode, start bit and stop bit is not attached to the data byte. 12.4.2 uart clock selection (1) dedicated baud rate generator when a dedicated baud rate generator is selected, the following baud rates are used: note: ? : machine clock div: division ration please refer to chaper 11, communication prescaler. table 12.4.1a uart operation modes mode parity data length operation mode stop bit length 0 yes/no 7 asynchronous normal mode 1 bit or 2 bits yes/no 8 1no8 + 1 asynchronous multi-processor mode 2 no 8 clk synchronous mode no table 12.4.2a baud rate (f indicates the machine clock.) cs2 cs1 cs0 asynchronous calculation 000 9615 ( ?? div) / (8 132) 001 4808 ( ?? div) / (8 132 2 ) 010 2404 ( ?? div) / (8 132 3 ) 011 1202 ( ?? div) / (8 132 4 ) 1 0 0 31250 ( ?? div) / 2 6 cs2 cs1 cs0 clk synchronous calculation 0001m ( ?? div) / 2 001 500 k ( ?? div) / 2 2 010 250 k ( ?? div) / 2 3 011 125 k ( ?? div) / 2 4 100 62.5 k ( ?? div) / 2 5 12.4 operations MB90580 series chapter 12: uart 133 (2) internal timer when '110' is set in cs2 to cs0 and an internal timer is selected, the 16-bit timer (timer 0) is used in reload mode. the baud rate is calculated as described below in this case: asynchronous: ( ?? n)/(16 2 (n+1)) clk synchronous: ( ?? n)/(2 (n+1)) ? : machine clock n: timer count clock sourc n: timer reload value table 12.4.2b lists the baud rates and reload values (decimal) at a machine clock of 7,3728 mhz . when an internal timer (16-bit timer 0) is selected as a baud rate clock source, the 16-bit timer 0 output (tout0) is connected inside the controller. therefore, externally connecting the 16-bit timer 0 external pin (tot0) to the external clock input pin (sck0) of the uart is unnecessary. if the timer 0 output pin is not used for other purposes, it can be used as an i/o port pin. (3) external clock when '111' is set in cs2 to cs0 and an external clock is selected, the baud rate can be expressed as described below, assuming f to be the external clock frequency: asynchronous: f/16 clk synchronous: f note: f is up to 1 mhz. table 12.4.2b baud rates and reload values n=2 1 (machine clock/2) n=2 3 (machine clock/8) 38400 2 19200 5 9600 11 2 4800 23 5 2400 47 11 1200 95 23 600 191 47 300 383 95 12.4 operations 134 chapter 12: uart MB90580 series 12.4.3 asynchronous mode (1) transfer data format uart handles nrx (non return to zero) format data only. figure 12.4.3a gives the data format. figure 12.4.3a transfer data format (modes 0 and 1) as shown in figure 12.4.3a, the transfer data always starts from the start bit ('l' level data), transfer is based on the data bit length specified by the first lsb, and transfer ends at the stop bit ('h' level data). when external clock is selected, ensure that the clock is input. in normal mode (mode 0), the data length can be 7 or 8 bits. in multi-processor mode (mode 1), the data length must be 8 bits. in multi-processor mode, no parity bit can be added. instead, the a/d bit is always added. (2) reception data is always received while '1' is written to the rxe bit (bit 9) of the scr register. when the start bit appears in the reception line, one frame of data is received according to the data format determined by the scr register. once a frame has been received, an error flag is set if an error has occurred, and the rdrf flag (bit 12 of the ssr register) is set. at that time, if '1' is written to the rie bit (bit 9) of the same ssr register, a reception interrupt is issued to the cpu. check the flags of the ssr register. read the sidr register if the reception has been normal. if an error has occurred, take appropriate measures. the rdrf flag is cleared when the sidr register is read. (3) transmission transmission data is written into the sodr register when '1' is set in the txe bit (bit 8) of the ssr register. then, if '1' is written to the txe bit (bit 8) of the scr register, transmission is performed. when the data set in the sodr register is loaded into the transmission shift register and transmission starts, the tdre flag is set again and the next transmission data item can be set. at that time, if '1' is written to the tie bit (bit 8) of the same ssr register, a transmission interrupt is issued to the cpu, requesting to set the transmission data in the sodr register. the tdre flag is cleared when data is written to the sodr register. (mode 0) (mode 1) 01001101 b is transferred. sin0, sot0 01 start lsb msb stop a/d stop 00001 1 1 1 1 12.4 operations MB90580 series chapter 12: uart 135 12.4.4 clk synchronous mode (1) transfer data format uart handles nrx (non return to zero) format data only. figure 12.4.4a shows the transmission/reception clock and data. figure 12.4.4a transfer data format (mode 2) when the internal clock (dedicated baud rate generator or internal timer) is selected, a data reception synchronization clock is automatically generated upon data transmission. when an external clock is selected, it is necessary to supply precisely one byte of clock after it is confirmed that the transmission data buffer (sodr register) of the transmission uart contains data (the tdre flag is '0'). ensure that the signal is at the mark level before and after transmission. only 8-bit data can be handled, and no parity bit can be added. since there is no start or stop bits, no errors are detected except for an overrun error. (2) initialization the control register values for clk synchronous mode are listed below. ? smr register md1 and md0 : 10 cs2, cs1, and cs0: clock input scke : dedicated baud rate generator or internal timer: 1external clock: 0 soe : transmission and reception: 1 reception only: 0 - scr register pen : 0 p, sbl, a/d : invalid cl : 1 rec : 0 (to be initialized) rxe and txe : 1 written to one or both ? ssr register rie : interrupts are enabled: 1 interrupts are disabled: 0 tie : 0 sodr write mark (mode 2) 01001101 b is transferred. sclk rxe, txe sin0, sot0 1011 10 0 0 msb lsb 12.4 operations 136 chapter 12: uart MB90580 series (3) start of communication communication is started by writing data in the sodr register. virtual transmission data must be writ- ten to the sodr register even when only reception is to be performed. (4) end of communication the end of communication can be checked by '1' written to the rdrf flag of the ssr register. use the ore bit of the ssr register to check whether communication has been successful. 12.4 operations MB90580 series chapter 12: uart 137 12.4.5 interrupt occurrence and flag set timing uart has five flags and two interrupt causes. the five flags are pe, ore, fre, rdrf, and tdre. pe indicates a parity error, ore indicates an overrun error, and fre indicates a framing error. these three flags are set when the corresponding error occurs during reception, and are cleared when '0' is written to rec of the scr register. rdrf is set when the received data is loaded into the sidr register, and is cleared when the sidr register is read. the parity detection function is not available in mode 1, and the parity and framing error detection functions are not available in mode 2. tdre is set when the sodr register becomes empty and can be written to. tdre is cleared when the sodr register is written to. the two interrupt causes are for reception and transmission. during reception, an interrupt is requested by pe, ore, fre, and rdrf. during transmission, an interrupt is requested by tdre. the timing to set interrupt flags in each operation mode is described below. (1) reception in mode 0 the pe, ore, fre, and rdrf flags are set when reception is completed and the last stop bit is detected. then, an interrupt request is issued to the cpu. if the pe, ore, and fre flags are active, the data in sidr is invalid. figure 12.4.5a timing to set pe, ore, fre, and rdrf (mode 0) (2) reception in mode 1 the ore, fre, and rdrf flags are set when reception is completed and the last stop bit is detected. then, an interrupt request is issued to the cpu. since the receivable data length is eight bits, the ninth bit indicating the address and data is invalid. if the ore and fre flags are active, the data in sidr is invalid. figure 12.4.5b timing to set ore, fre, and rdrf (mode 1) (3) reception in mode 2 the ore and rdrf flags are set when reception is completed and the last data item (d7) is detected. data reception interrupt d6 d7 stop pe, ore, fre rdrf data reception interrupt d7 stop ore, fre rdrf address/data 12.4 operations 138 chapter 12: uart MB90580 series then, an interrupt request is issued to the cpu. if the ore flag is active, the data in sidr is invalid. figure 12.4.5c timing to set ore and rdrf (mode 2) (4) transmission in modes 0, 1, and 2 tdre is cleared when a data item is written into the sodr register. when the data item is transferred to the internal shift register and the next data item can be written, tdre is set and an interrupt request is issued to the cpu. if '0' is set in txe (or additionally rxe in mode 2) of the scr register during transmission, '1' is set in tdre of the ssr register. then, the transmission shifter stops and the transmission by uart is disabled. if '0' is set in txe (or additionally rxe in mode 2) of the scr reg- ister during transmission, the data set in the sodr register is transmitted before transmission stops. figure 12.4.5d timing to set tdre (modes 0 and 1) figure 12.4.5e timing to set tdre (mode 2) data reception interrupt d5 d6 d7 ore rdrf st d0 d1 d2 d3 d4 d5 d6 d7 sp a/d sp st d0 d1 d2 d3 tdre st: startbit d0 to d7: databits sp: stopbit sodr write sot0 interrupt sot0 output an interrupt request is issued to the cpu. a/d: address/data multiplexer d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 tdre d4 d5 d6 d7 sodr write sot0 interrupt sot0 output an interrupt request is issued to the cpu. d0 to d7: data bits 12.4 operations MB90580 series chapter 12: uart 139 12.4.6 i 2 os (intelligent i/o service) for i 2 os, see the section describing i 2 os. 12.4.7 notes on use to set a communication mode, ensure that uart is not in operation. the data sent or received during mode setting is not guaranteed. 12.4.8 application mode 1 is used when two or more slave cpus are connected to a single host cpu (see figure 12.4.8a). this resource only supports the host side communication interface. figure 12.4.8a sample system configuration in mode 1 communication starts when the host cpu transfers address data. address data means the data used when '1' is set in a/d of the scr register. the address data determines the destination slave cpu and enables communication between the host and slave cpus. ordinary data means the data used when '0' is set in a/d of the scr register. figure 12.4.8b shows the flowchart. in mode 1, the parity check function cannot be used. therefore, set '0' in the pen bit of the scr register. slave cpu #0 slave cpu #1 so si so si host cpu si so 12.4 operations 140 chapter 12: uart MB90580 series figure 12.4.8b flow chart of communication in mode 1 start no yes end no yes (host cpu) select transfer mode 1. set the data for selecting the slave set '0' in a/d. reception is enabled. communication with the slave cpu end communication? communicate with reception is disabled. cpus in d0 to d7 and set '1' in a/d to transfer one byte. other slave cpu? chapter 13: ie bus 13.1 outline iebus (inter equipment bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. it is designed for use in automotive and general industrial applications. the communication protocol of the iebus has the following features: ? multi-master method all the units connected to the iebus can transfer data to the other units. ? multiaddress communication function (one unit can communicate to two or more units simultaneously) group communication: multiaddress communication to group unit broadcasting communication: multiaddress communication to all units ? three different transfer rates can be selected: ? transmit data buffer : 8-byte fifo ? receive data buffer : 8-byte fifo ? cpu internal operation frequency: 12 mhz, 12.58 mhz mode ie bus internal frequency at 6 mhz ie bus internal frequency at 6 mhz 0 approx. 3.9 kbps approx. 4.1 kbps 2 approx. 17 kbps approx. 18 kbps 3 approx. 26 kbps approx. 27 kbps 13.2 block diagram 142 chapter 13: ie bus MB90580 series 13.2 block diagram figure 13.2a block diagram of ie bus uuit address register f2mc-16lx bus slave address register multiaddress control bit set register telegraph length set register write data buffer (8-byte fifo) master address read register multiaddress control bit read register telegraph length set register read dta buffer (8-byte fifo) lock read register status register command register control circuitry ie protocol controller prescaler 2 interrupt request (transmit, receive) internal clock tx rx note: function of control circuitry 1. control the number of transmit/receive bytes 2. control max. number of byte transmission 3. detect arbitration 4. determine acknowledgement 5. generate interrupt (12 mhz / 12.58 mhz) (6 mhz / 6.29 mhz) 13.3 registers and register details MB90580 series chapter 13: ie bus 143 13.3 registers and register details figure 13.3a registers of ie bus (1/3) tie gotm rie 15 14 13 12 11 10 9 8 pcom md1 md0 cmrh address: 000077 h gots reserved (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (x) (r/w) (0) bit number command register upper byte (cmrh) cs1 cs0 tit0 tit1 cmrl address: 000076 h rxs txs (r/w) (1) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (0) (r/w) (0) bit number. 76543210 rdbc wdbc command register lower byte (cmrl) read/write initial value ma11 ma10 15 14 13 12 11 10 9 8 mawh address: 000071 h reserved reserved (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) bit number mawl address: 000070 h (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 reserved reserved ma09 ma08 ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 unit address register (mawh, mawl) sa11 sa10 15 14 13 12 11 10 9 8 sawh address: 000073 h reserved reserved (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) sawl address: 000072 h (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 reserved reserved sa09 sa08 sa07 sa06 sa05 sa04 sa03 sa02 sa01 sa00 slave address register (sawh, sawl) bit number bit number bit number read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value 13.3 registers and register details 144 chapter 13: ie bus MB90580 series figure 13.3b registers of ie bus (2/3) c3 c2 do0 15 14 13 12 11 10 9 8 do1 do3 do2 dcwr address: 000075 h (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) c1 c0 mutliaddress, control bit set register (dcwr) bit number bit number de3 de2 de4 de5 decr address: 000074 h (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 7 65 43210 de1 de0 de6 de7 telegraph length set register (dewr) bit number rif tif ack 15 14 13 12 11 10 9 8 pef com te strh address: 000079 h (r) (0) (r) (x) (r/w) (0) (r) (0) (r) (x) (r/w) (0) (r) (0) (r/w) (0) tsl eod status register upper byte (strh) bit number st3 st2 rdbe wdbe strl address: 000078 h 76543210 st1 st0 rdbf wdbf (r) (0) (r) (0) (r) (1) (r) (1) (r) (x) (r) (x) (r) (x) (r) (x) status register lower byte (strl) bit number ld11 ld10 15 14 13 12 11 10 9 8 lrrh address: 00007b h reserved reserved (r) (1) lrrl address: 00007a h 7 65 43210 reserved ld09 ld08 ld07 ld06 ld05 ld04 ld03 ld02 ld01 ld00 loc (r) (1) (r/w) (1) (r) (0) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) lock read register (lrrh, lrrl) bit number read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 145 figure 13.3c registers of ie bus (3/3) ma11 ma10 15 14 13 12 11 10 9 8 marh address: 00007d h reserved reserved marl address: 00007c h 76543210 reserved ma09 ma08 ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 reserved (r) (1) (r) (1) (r) (1) (r) (1) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) master address read register (marh, marl) bit number bit number bit number c3 c2 do0 do1 dcrr address: 00007f h 15 14 13 12 11 10 9 8 c1 c0 do2 do3 (r) (0) (r) (0) (r) (0) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) multiaddress, control bit read register (dcrr) bit number de3 de2 de4 de5 derr address: 00007e h 76543210 de1 de0 de6 de7 (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) telegraph length read register (derr) bit number bit number rd3 rd2 rd4 rd5 rdb address: 000081 h 15 14 13 12 11 10 9 8 rd1 rd0 rd6 rd7 (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) read data buffer (rdb) wd3 wd2 wd4 wd5 wdb address: 000080 h 76543210 wd1 wd0 wd6 wd7 (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) write data buffer (wdb) (w) (x) read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value 13.3 registers and register details 146 chapter 13: ie bus MB90580 series 13.3.1 command register upper byte (cmrh) [bits 15 and 14] md1, md0 (mode select): these bits are used to select the iebus operation mode. [bit 13] pcom (communication enable): this bit is used to enable iebus communication. when pcom is written 1, the com flag in status register (strh) is set and then the communication is enabled. when pcom is written 0, the communication is ended. please set this bit to 1 if the com flag in the status register is 0. [bit 12] rie (receive interrupt enable): this bit controls receive interrupt as described below. the receive interrupt is occurred under the following condition: ? the eight byte receive data buffer (rdb) is full. ? data reception is finished normally. ? the communication has ended without receiving the number of data specified by telegraph length field in one communication frame. ? when arbitration lost, the unit cannot be selected as slave unit. table 13.3.1a transmission mode md1 md0 operation mode 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 setting inhibited tie gotm rie 15 14 13 12 11 10 9 8 pcom md1 md0 cmrh address: 000077 h gots reserved (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (x) (r/w) (0) bit number command register upper byte (cmrh) read/write initial value 0 receive interrupt disabled 1 receive interrupt enabled 13.3 registers and register details MB90580 series chapter 13: ie bus 147 [bit 11] tie (transmit interrupt enable): this bit controls transmit interrupt as described below. the transmit interrupt is occurred under the following condition: ? in master transmit, after master address field has been transmitted, the master unit has won in arbitration. ? in slave transmit, the control bits requesting for data transmit are received from master unit. ? writing the number of data bytes (controlled by tit1, tit0 bits of command register, cmrl) into write data buffer (wdb) is requested. ? transmission of the number of data specified by telegraph length field has been completed in one communication frame. ? the communication has ended without transmitting the number of data specified by telegraph length field in one communication frame. [bit 10] gotm (master transmit): this bit indicates the start of transmission. after the communication inhibit state has been released, when gotm is set to 1, data transmission begins. this bit is written 1 only and alwaays read 0. writing 0 to this bit has no meaning. [bit 9] gots (slave transmit): this bit indicates the start of transmission. after the communication inhibit state has been released, when gots is set to 1, data transmission begins. this bit is written 1 only and always read0. writing 0 to this bit has no meaning. [bit 8] reserved bits always write 1 to this bit and the read value is undefined. table 13.3.1b setting for gotm and gots gotm gots abritration slave transmit operation 0 0 none not allowed slave receive 0 1 none allowed slave transmit 1 0 present not allowed after abritration lost, it can change to slave receive 1 1 present allowed after abritration lost, it can change to slave transmit 0 transmit interrupt disabled 1 transmit interrupt enabled 13.3 registers and register details 148 chapter 13: ie bus MB90580 series 13.3.2 command register lower byte (cmrl) [bit 7] rxs rx input pin polarity selected for external driver/receiver. [bit 6] txs tx output pin polarity selected for external driver/receiver. note1: for MB90580 series, during reset, tx pin will output l. if the driver/receiver used is in positive logic (driver/receiver enable at l), tx outputs l from reset to bit setting that will generate a communication error when there is a communication between other communication units. when it happens, it needs a outside circuit to input h to the driver/receiver from reset to bit setting. [bit 5, 4] tit1, tit0 (data transmit interrupt control bits) these bits control the time interval of the occurrence of interrupt for writing transmit data in write data buffer (wdb). table 13.3.2a interval for the occurrence of data transmit interrupt rxs rx input status 0 rx pin as postive logic input. logic 1 is high level and logic 0 is low level. 1 rx pin as negative logic input. logic 1 is low level and logic 0 is high level. table 13.3.2b interval for the occurrence of data transmit interrupt txs tx output 0 tx pin as postive logic output. logic 1 is high level and logic 0 is low level. 1 tx pin as negative logic output. logic 1 is low level and logic 0 is high level. table 13.3.2c interval for the occurrence of data transmit interrupt tit1 tit0 timing for interrupt occurs 0 0 more than one byte data can be written in wdb 0 1 more than two byte data can be written in wdb 1 0 more than four byte data can be written in wdb 1 1 eight byte data can be written in wdb cs1 cs0 tit0 tit1 cmrl address: 000076 h rxs txs (r/w) (1) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (1) (r/w) (0) (r/w) (0) bit number. 76543210 rdbc wdbc command register lower byte (cmrl) read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 149 [bit 3, 2] cs1, cs0 (cycle select): these bits control both the cpu internal clock cycle and iebus controller clock cycle and cs1 and cs0 must be set to 0. . note1: the cpu and iebus internal clock frequency are calculated by the above equation provided that the cpu operating frequency is inside the guaranteed range. note2: the accuracy of clock cycle calculation for mode 0 and 1 is 1.5%, and for mode 2 is 0.5%. [bit 1] rdbc (read data buffer clear): this bit is used to clear the 8-byte read data buffer, rdb. when this bit is set to 1, all the eight bytes in rdb are cleared. (rdbe = 1) this bit is always read as 0. [bit 0] wdbc (write data buffer clear): this bit is used to clear the 8-byte write data buffer, wdb. when this bit is set to 1, all the eight bytes in wdb are cleared and wdb becomes empty (wdbe = 1 ) this bit is alwarys read as 0. for the communication with no. of byte transfer greater than the maximum transfer byte per frame, the data written in the previous frame will no longer valid if 1 is written to this bit. the data written in the current frame will be transmitted first. in converse, if 0 is written to this bit, the unsent data in the pre- vious frame will be prioritized to be sent first. if the transmission is terminated due to timing error, even thought 0 is written to this bit, the transmis- sion will be started from the next data and not the last one which has not been sent completely. table 13.3.2d internal clock frequency cs1 cs0 cpu internal clock f iebus internal clock equation 00 12mhz (12.58 mhz) 6mhz(6.29mhz) f ie = f /2 0 1 setting inhibited ---- ---- 1 0 setting inhibited ---- ---- 1 1 setting inhibited ---- ---- 13.3 registers and register details 150 chapter 13: ie bus MB90580 series 13.3.3 unit address register (mawh, mawl) these two registers mawh, mawl are used to set its own unit address (12 bits). when the unit is config- ured as master, the unit address set in mawh, mawl is transmitted as master address. when it is config- ured as slave mode, this unit address is used to compare with the received slave address. bit 15 to 12 are reserved bits and always write 1 to them. the read values are undefined. note: make sure to set the unit address before the communication inhibit state is released. 13.3.4 slave address register (sawh, sawl) these two registers sawh, sawl are used to set the slave address (12 bits) for master transmit. bit 15 to 12 are reserved bits and always write 1 to them. the read values are undefined. note: make sure to set the slave address before the communication inhibit state is released. ma11 ma10 15 14 13 12 11 10 9 8 mawh address: 000071 h reserved reserved (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) bit number mawl address: 000070 h (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 7 65 43210 reserved reserved ma09 ma08 ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 unit address register (mawh, mawl) bit number read/write initial value read/write initial value sa11 sa10 15 14 13 12 11 10 9 8 sawh address: 000073 h reserved reserved (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) sawl address: 000072 h (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) 76543210 reserved reserved sa09 sa08 sa07 sa06 sa05 sa04 sa03 sa02 sa01 sa00 slave address register (sawh, sawl) bit number bit number read/write initial value read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 151 13.3.5 mutliaddress, control bit set register (dcwr) [bit 15, 14, 13, 12] do3, do2, do1, do0 (multiaddress/normal communication select bits): these bits are used to select multiaddress (more than one slave) or normal communication (one slave). for multiaddress communication, do3-0 is set to 0000 and then the multiaddress bit in communica- tion frame is sent out as 0. for normal communication, do3-0 is set to 1000 and then the multiaddress bit in communication frame is sent out as 1. always write 0 to bit 14, 13, and 12, and when reading, these bits always return 0. [bit 11, 10, 9, 8] c3, c2, c1, c0 (control bits): these bits are used to control iebus communication. note1: the transfer direction of telegraph length bits in telegraph length field and data bits in data field are controlled by the value of c3 as follows: when c3 is 1: transfer from master unit to slave unit when c3 is 0: transfer from slave unit to master unit note2: 3h, 6h, ah, bh are the lock and unlock function selection bits. note3: when sending the undefined control bits like 1h, 2h, 8h, 9h, ch, dh, no acknowledge will be returned. table 13.3.5a control bits setting c3 note 1 c2 c1 c0 control operation 0h 0 0 0 0 slave status read 1h 0 0 0 1 undefined 2h 0 0 1 0 undefined 3h 0 0 1 1 data read and lock 4h0100 lock address read (lower 8 bits) 5h0101 lock address read (upper 4 bits) 6h 0 1 1 0 slave status read and unlock 7h0111data read 8h 1 0 0 0 undefined 9h 1 0 0 1 undefined ah 1 0 1 0 command write and lock bh 1 0 1 1 data write and lock ch 1 1 0 0 undefined dh 1 1 0 1 undefined eh 1 1 1 0 command write fh 1 1 1 1 data write c3 c2 do0 15 14 13 12 11 10 9 8 do1 do3 do2 dcwr address: 000075 h (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) c1 c0 mutliaddress, control bit set register (dcwr) bit number read/write initial value 13.3 registers and register details 152 chapter 13: ie bus MB90580 series 13.3.6 telegraph length set register (dewr) this register is used to set the number of data bytes to be transmitted and is valid only for data transmission. during slave transmit, make sure to set the transmit data count byte to 1 when the control frame are 0h (reading slave status), 4h (reading lock-address of the lower 8-bit), 5h (reading lock-address of the upper 8-bit), 6h (reading slave -status and diabling lock). if the no. of bytes required to transfer is greater than the maximum no of transfer byte per frame, it will result in multiframe communciation. in that case, dewr should be set using the following formula. dewr = derr - maximum no. of transfer bytes per frame upon the completion of one frame, the remaining number of byte required to transfer can be obtained by deducting the maximum no. of transfer byte per frame from derr. this value is used to set dewr for the next frame. table 13.3.6a number of transmit data bytes setting de7-0 number of transmit data bytes 01h 1 byte 02h 2 bytes .. .. .. .. ffh 255 bytes 00h 256 bytes bit number de3 de2 de4 de5 decr address: 000074 h (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) 76543210 de1 de0 de6 de7 telegraph length set register (dewr) read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 153 13.3.7 status register upper byte (strh) [bit 15] com (communication status): this bit indicates the communication status as described below. when this bit is 0 and the pcom bit in command register (cmrh) is written 1, this bit is set. when communication ends, this bit will be cleared. . [bit 14] te (timing error): this bit is set when timing error has occurred during communication. writing 0 will clear this bit. this bit is written 0 only, there is no meaning for writing 1. [bit 13] pef (parity error): this bit is set when parity error has been detected. in receive side, if this bit is set, the acknowledge bit will not be returned. this bit will be cleared after the communication inhibit state is released. [bit 12] ack (acknowledge bit): this bit indicates during normal communication, acknowlege bit will be returned after each data received correctly. this bit will be cleared after communication inhibit state is released. this bit has no meaning in multiaddress communication and the read value is indefined. bit number rif tif ack 15 14 13 12 11 10 9 8 pef com te strh address: 000079 h (r) (0) (r) (x) (r/w) (0) (r) (0) (r) (x) (r/w) (0) (r) (0) (r/w) (0) tsl eod status register upper byte (strh) read/write initial value 0 communication is prohibited 1 communication is enabled 0 no parity error 1parity error 0 the acknowledge bit is 0 1 the acknowledge bit is 1 13.3 registers and register details 154 chapter 13: ie bus MB90580 series [bit 11] rif (receive interrupt flag): this bit is set when receive interrupt is occurred. this bit is cleared by writing 0 to this bit or after the extended intelligent i/o service has been served. this bit is written 0 only. [bit 10] tif (transmit interrupt flag): this bit is set when transmit interrupt is occurred. this bit is cleared by writing 0 to this bit or after the extended intelligent i/o service has been served. this bit is written 0 only. [bit 9] tsl (transmit limit): this bit is set when the maximum number of data bytes that can be transmitted in one communication frame has been reached. and this bit is cleared when next communication frame starts. [bit 8] eod (end of data): this bit is set when the number of data bytes specified by telegraph length field has been transferred completely. it means communication ends normally. this bit is cleared when next communication frame starts. 0 no receive interrupt request 1 have receive interrupt request 0 no transmit interrupt request 1 have transmit interrupt request 13.3 registers and register details MB90580 series chapter 13: ie bus 155 13.3.8 status register lower byte (strl) [bit 7] wdbf (write data buffer full): this flag indicates the status of the write data buffer (wdb). this bit is set when wdb is full and cleared when at least one byte of data can be written into wdb. [bit 6] rdbf (read data buffer full): this flag indicates the status of the read data buffer (rdb). this bit is set when rdb is full and cleared when at least one byte of data can be received and stored in rdb. [bit 5] wdbe (write data buffer empty): this flag indicates the status of the write data buffer (wdb). this bit is set when wdb is empty and cleared when data is written into wdb. writing 1 to wdbc in command register cmrl will set this bit. [bit 4] rdbe (read data buffer empty): this flag indicates the status of the read data buffer (rdb). this bit is set when rdb is empty and cleared when data is received and stored in rdb. writing 1 to rdbc in command register cmrl will set this bit. bit number st3 st2 rdbe wdbe strl address: 000078 h 76543210 st1 st0 rdbf wdbf (r) (0) (r) (0) (r) (1) (r) (1) (r) (x) (r) (x) (r) (x) (r) (x) status register lower byte (strl) read/write initial value 0 write data buffer is not full 1 write data buffer is full 0 read data buffer is not full 1 read data buffer is full 0 write data buffer is not empty 1 write data buffer is empty 0 read data buffer is not empty 1 read data buffer is empty 13.3 registers and register details 156 chapter 13: ie bus MB90580 series [bit 3-0] st3, st2, st1, st0 (operation status bits) these bits indicates the communication status of the unit and generates the corresponding interrupt during transmission or reception. by reading these bits, the communication status of the unit can be known. for more detail description on setting these four bits, please refer to table 13.5.2a. table 13.3.8a status flag st3 st2 st1 st0 status state 0000 master/slave trans- mit transmit starts 0 0 0 1 during transmission 0 0 1 0 transmit ends normally 0 0 1 1 ends without all data being transmitted 0100 master receive master receive starts 0 1 0 1 master receive data full 0 1 1 0 master receive ends normally 0 1 1 1 ends without all data being received 1000 slave receive slave receive starts 1 0 0 1 slave receive data buffer full 1 0 1 0 slave receive ends normally 1 0 1 1 ends without all data being received 1100 multiaddress receive multiaddress receive starts 1 1 0 1 multiaddress receive data buffer full 1 1 1 0 multiaddress receive ends normally 1 1 1 1 ends without all data being received 13.3 registers and register details MB90580 series chapter 13: ie bus 157 13.3.9 lock read register (lrrh, lrrl) [bit 15-13] reserved bits: always reading 1 from these bits. [bit 12] loc (lock check): this bit indicates the status whether the unit is locked or not from other unit. writing 0 to this bit will unlock the unit itself. writing 1 to this bit has no meaning. [bit 11-0] ld11 - ld00 (lock address): these bits store the lock address, the address of the master that has executed locking to the unit. when the unit is not locked. there is no meaning for these bits. note: in iebus communication, the lock function is used to transmit a message over two or more communication frames. if the master that has executed locking was down before executing the unlocked command, the locked unit cannot receive data anymore. so in order to prevent such condition, the unit in the system that supporting lock function need checking the lock status periodically by reading this lock read register. and the unit can unlock itself by writing 0 to loc bit.. bit number ld11 ld10 15 14 13 12 11 10 9 8 lrrh address: 00007b h reserved reserved (r) (1) lrrl address: 00007a h 76543210 reserved ld09 ld08 ld07 ld06 ld05 ld04 ld03 ld02 ld01 ld00 loc (r) (1) (r/w) (1) (r) (0) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) lock read register (lrrh, lrrl) bit number read/write initial value read/write initial value 0does not lock 1 locked 13.3 registers and register details 158 chapter 13: ie bus MB90580 series 13.3.10 master address read register (marh, marl) [bit 15 - 12] reserved bits: always reading 1 from these bits. [bit 11 - 0] ma11 - ma00 (master address): in slave mode, these bits store the address of the master that has won the arbitration in master address field. if the unit itself is the master, then the unit address stored in unit address register (mawh, mawl) will be read out. ma11 ma10 15 14 13 12 11 10 9 8 marh address: 00007d h reserved reserved marl address: 00007c h 76543210 reserved ma09 ma08 ma07 ma06 ma05 ma04 ma03 ma02 ma01 ma00 reserved (r) (1) (r) (1) (r) (1) (r) (1) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) master address read register (marh, marl) bit number bit number read/write initial value read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 159 13.3.11 multiaddress, control bit read register (dcrr) [bit 15-12] do3, do2, do1, do0 (multiaddress/normal communication bits): in slave mode, the received multiaddress bit from the master is stored in bit do0. if the unit itself is the master, the multiaddress/normal communication set bits (do3-0) in multiaddress, control bit set register (dcwr) is read out. normal communction: (0001 b ) multiaddress communication: (0000 b ) do3~0 always read as 0. [bit 11-8] c3, c2, c1, c0 (control bits) in slave mode, the received control bits from the master are stored in these bits. if the unit itself is the master, the control bits (c3-0) in multiaddress, control bit set register (dcwr) is read out. these bits are set after the control field has been received and acknowledge bit was detected. for more detail description, please refer to table 13.3.5a. bit number c3 c2 do0 do1 dcrr address: 00007f h 15 14 13 12 11 10 9 8 c1 c0 do2 do3 (r) (0) (r) (0) (r) (0) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) multiaddress, control bit read register (dcrr) read/write initial value 13.3 registers and register details 160 chapter 13: ie bus MB90580 series 13.3.12 telegraph length read register (derr) if the unit itself is the receiver, this register stores the number of data specified by telegraph length field. if the unit itself is the transmitter, the telegraph length bits in telegraph length set register (dewr) are read. this register is set after the following. 1. when used as master unit (a) in transmit mode, the number of transmit data bytes is written into dewr (b) in receive mode, the telegraph length field is received (c) communication ends 2. when used as slave unit (a) in transmit mode, the number of transmit data bytes is written into dewr (b) in receive mode, the telegraph length field is received (c) communication ends bit number de3 de2 de4 de5 derr address: 00007e h 76543210 de1 de0 de6 de7 (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) telegraph length read register (derr) read/write initial value 13.3 registers and register details MB90580 series chapter 13: ie bus 161 13.3.13 read data buffer (rdb) this register (internally is a 8-byte fifo buffer) stores received data in data field of the communication frame. when eight byte data have been received, rdb becomes full and receive interrupt is generated. then data in rdb should be read out before the next coming byte of data is received as shown in table 13.3.13a . otherwise, error will be occurred. when error occurs in multiaddress reception, the communication ends. but when error occurs in normal reception, the acknowledge bit will not returned to the transmitter. then the transmitter will resend data again until the maximum number of data transmitted is reached. even though rdb is not full, the receive interrupt will be generated when the number of data specified in the telegraph field have been received, or the maximum number of data received in one communication frame is reached. once the receive interrupt has occurred, the data in rdb should be read out. writing 1 to wdbc in cmrl will clear all data in the buffer and return it as empty state. this register can only be read when noit empty table 13.3.13a time required for next data receive after receive buffer full interrupt occurred maximum time (us) no. of cycles mode 0 1580 19000 mode 1 400 4800 mode 2 290 3400 bit number rd3 rd2 rd4 rd5 rdb address: 000081 h 15 14 13 12 11 10 9 8 rd1 rd0 rd6 rd7 (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) (r) (x) read data buffer (rdb) read/write initial value 13.3 registers and register details 162 chapter 13: ie bus MB90580 series 13.3.14 write data buffer (wdb) this register (internally is a 8-byte fifo buffer) stored data to be transmitted in data field of the communication frame. the data write interrupt timing is set by the two bits tit1, tit0 in command register (cmrl). when the write interrupt occurs, next data is requested to write into wdb. when all data has been trans- mitted (wdb is empty), and the data cannot be writtenin rdb within the time listed in table 13.3.14a, it will result in an error and the transmission will be terminated. writing 1 to wdbc bit in command register cmrl will clear the buffer and return it as empty state. this register can only be written when not full. table 13.3.14a data write time after wdb empty interrupt maximum time no. of cycles mode 0 1580 19000 mode 1 400 4800 mode 2 290 3400 bit number wd3 wd2 wd4 wd5 wdb address: 000080 h 76543210 wd1 wd0 wd6 wd7 (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) (w) (x) write data buffer (wdb) (w) (x) read/write initial value 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 163 13.4 iebus communication protocol 13.4.1 overview iebus (inter equipment bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. ? communication method data are transferred by means of half duplex asynchronous communication. ? multi-master method all the units connected to the iebus can transfer data to the other units. ? multiaddress communication function (one unit can communicate to two or more units simultaneously) group communication: multiaddress communication to group units broadcasting communication: multiaddress communication to all units ? three transfer rates can be selected: ? access control: csma/cd (carrier sense multiple access with collision detection) ? the priority to occupy the iebus: (1) multiaddress communication takes precedence over normal communication (communication between one unit and another). (2) the lower master address takes precedence over the higher address. ? communication scale note number of units: 50 max. cable length: 150m max. (when twisted pair cable with resistance less than 0.1 w/m is used) loading capacitance: 8000pf max. (between bus- and bus+) when iebus internal clock is 6 mhz 7100pf max. (between bus- and bus+) when iebus internal clock is 6.29mhz terminal resistance: 120 w. note: the system sacle depends on the ie bus driver/receiver that is used. table 13.4.1a iebus transfer rates mode iebus internal clock = 6mhz iebus internal clock = 6.29mhz maximum number of transfer bytes (bytes / frame) 0 approx. 3.9kbps approx. 4.1 kbps 16 1 approx. 17kbps approx. 18 kbps 32 2 approx. 26kbps approx. 27kbps 128 13.4 iebus communication protocol 164 chapter 13: ie bus MB90580 series 13.4.2 determining bus mastership (arbitration) the equipment connected to the iebus performs an operation to occupy the bus when it controls another equipment. this operation is called arbitration. arbitration is to grant the bus mastership to one of several units that have simultaneously started transmission. as only one equipment acquires the bus mastership as a result of arbitration, the following priority is used to determine which equipment acquires the bus mastership: ? priority on type of communication multiaddress communication takes precedence over normal communication. ? priority on master address if the type of communication is the same, the lower master address takes precedence over the higher one. example: the master address consists of 12 bits, the unit at 000h has the highest priority, and the unit at fffh has the lowest priority. 13.4.3 communication mode the iebus provides three communication modes, in which each has a different transfer rate. the transfer rate in each communication mode and the maximum number of transfer bytes in one communication frame are shown as below: note1: effective transfer rate is measured when the maximum number of data bytes have been transferred. note2: the relationship between iebus internal clock and cpu clock is referred to table 13.3.2d. caution1: the required communication mode should be selected for each equipment connected to the iebus before communication is started. also, the communication is not performed correctly unless the communication mode of the master and the slave unit are the same. caution2: be sure that both the communication mode and iebus internal clock are the same for all units connected to the iebus. even though the same communication mode is selected, the communication is still performed incorrectly if the iebus internal clock frequency is different. table 13.4.3a transfer rate and maximum number of transfer byte in each communication mode mode maximum number of transfer bytes (bytes / frame) effective transfer rate (bps) note1 iebus internal clock = 6mhz note2 iebus internal clock = 6.29 mhz note2 0 16 approx. 3.9kbps approx. 4.1 kbps 1 32 approx. 17kbps approx. 18 kbps 2 128 approx. 26kbps approx. 27kbps 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 165 13.4.4 communication address in iebus, each equipment is assigned to a specific 12-bit communication address. the communication address is consisted of: higher 4 bits:group number (identify which group the equipment belongs to) lower 8 bits:unit number (identify each equipment in one group) 13.4.5 multiaddress communication in normal communication mode, the communication is performed on a one-to-one basis, i.e. only one master and one slave. in contrast, multiaddress communication allows the master transmitting data to more than one slave. as more than one slave exist in the iebus, none of them returns an acknowledge sig- nal in the communication. the multiaddress bit is used to select either multiaddress communication or normal communication. for detail description, refer to (6) transfer protocol. multiaddress communication has the following two modes: ? group multiaddress communication communicating with equipments having the same group number as specifying in higher 4 bits of the communication address. ? broadcasting communication communicating with all equipments, regardless of the value of the group number the slave address specified in slave address field is used to identify either group multiaddress or broadcasting communication. for detail description, refer to section section 13.4.6, transfer protocol". 13.4 iebus communication protocol 166 chapter 13: ie bus MB90580 series 13.4.6 transfer protocol the signal transmit format of the iebus is shown as below note1: p: parity bit a: acknowledge bit where a=0: ack and a=1: nak note2: the acknowledge bit is ignored in multiaddress communication. (1) header the header field is consisted of start bit and multiaddress bit. ? start bit the start bit is a signal used to inform the other units that data transmission starts. the unit initiating the data transmission outputs a low-level signal (start bit) for a specific time and then outputs the multiaddress bit. when one unit tries to output the start bit, but it found that another unit has already output a start bit, then the unit does not output the start bit. but it waits for the end of the start bit output by the another unit and outputs the multiaddress bit in synchronization with the output end timing of the start bit. the units other than the one that has started transmission detect this start bit and enters the receive status. ? multiaddress bit this bit indicates whether the master selects multiaddress or normal communication. when the multiaddress bit is 0 for multiaddress communication and is 1 for normal communication. moreover, multiaddress communication is divided into two modes, group multiaddress and broadcasting communication. these two modes are identified by the value of the slave address. in multiaddress communication, since there are two or more slave units, the acknowledge bit for each field following the master field is not returned. if at the same time, two or more units start transmission of a communication frame, multiaddress com- munication takes precedence over normal communication and is the winner in arbitration. (2) master address field this field is outputted by the master to identify its address for other units being communicated and is consisted of 12 bit of master address with msb transmitting first and 1 parity bit. if at the same time, two or more units starts transmitting the multiaddress bit of the same value, judgement of arbitration is based on the master address field value. everytime when the unit transmits one bit of its unit address, it compares the data output with the data on the iebus. if they are found to be different, the unit lost the arbitration and then stops transmission and enters receive status. since the iebus is configured as wired and, the unit having the least master address among the units participating in arbitration (arbitration masters) wins arbitration. after 12-bit master address is transmitted out, only one unit remains in transmit status as the master. this master then outputs the parity bit and let other units confirming that the transmit master address data contains no error. after that, the slave address field is output. note: even parity is used for parity check. if the total number of 1 in master address bits is odd, the parity bit will be set as 1. header start bit multi- address bit p master address bits control bits slave address bits telegraph length bits data bits a pa p a p a p a p data bits master address field control field telegraph length field data field slave address field 1 1 12 1 12 1 1 4 11 8 1 1 811 811 approx. 7330 m s approx. 2090 m s approx. 1590 m s approx. 1590 x n m s approx. 410 x n m s approx. 300 x n m s field name no. of bits frame format mode 0 mode 1 mode 2 transmit time 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 167 (3) slave address field this field outputs the address of the other unit with which the master is to communicate and is consisted of 12 bits of slave address with msb transmitting first, parity bit and acknowledge bit. after a 12-bit slave address has been transmitted, a parity bit is output to ensure that the slave address is not received by mistake. then the master unit detects an acknowledge signal from slave unit to confirm its existence on the iebus. after the detection of acknowledge signal, the master unit starts outputting the control field. however in multiaddress communication mode, the master starts outputting the control field without detecting the acknowledge bit. in the slave side, when it detects that the slave address has coincided with its own unit address, and the parity bit in both master address field and slave address field are even, it outputs an acknowledge signal. however, if parity bit is odd, the slave unit judges that either master address or slave address has been received incorrectly, and then acknowledge signal is not returned. at this moment, the master unit enters the standby (monitor) status, and communication ends. in multiaddress communication mode, the slave address is used to identify whether it is group multiaddress or broadcasting communication as follows: when slave address is fffh: broadcasting communication when slave address is not fffh: group multiaddress communication note: the group number for group multiaddress communication is identified by the higher 4 bits of the slave address. (4) control field this field is used to control the type of following data field and direction of data transfer between master and slave. this field is consisted of 4 bits of control bit with msb transmitting first, parity bit and acknowledge bit. if even parity is checked and the slave can execute the function requested by the master, the slave returns an acknowledge signal and then proceeds to the telegraph length field. even though the parity is even, but if the slave unit cannot execute the function requested by the master, or if the parity is odd, the slave unit does not output the acknowledge signal and returns to the standby (monitor) status. after the master confirms the return of acknowledge signal, it proceeds to the telegraph length field. if the master cannot receive the acknowledge signal, it enters the standby status, and communication ends. in multiaddress communication mode, the master unit does not detect the acknowledge signal, but proceeds to the telegraph length field. (5) telegraph length field this field is used to indicate the number of bytes of transmit data from the transmitter to receiver. this field is consisted of 8 bits of telegraph length with msb transmitting first, parity bit and acknowledge bit. table 13.4.6a shows the relationship between the telegraph length field and the number of transmit data bytes. note: according to the communication mode being set, if the number of transmit data bytes set in telegraph length field is greater than the maximum number of transmit data bytes per frame, then communication with multi-frame is performed. in this table 13.4.6a number of transmit data bytes setting telegraph length bits (hex) number of transmit data bytes 01h 1 byte 02h 2 bytes .. .. .. .. ffh 255 bytes 00h 256 bytes 13.4 iebus communication protocol 168 chapter 13: ie bus MB90580 series case, the second and following communication frames will transmit the remaining data bytes specified in the telegraph length field. the function of telegraph length field differs when the master is in transmit mode (bit 3 of control bits is 1) or receive mode (bit 3 of control bits is 0) as follow: ? master transmit mode the telegraph length bits and parity bit are output by the master unit. if even parity is detected by the slave, it returns the acknowledge signal. then the master proceeds to the data field. but in multiad- dress communication mode, the slave does not return any acknowledge signal. if odd parity is detected, the slave judges that the telegraph length bits have not been correctly received, and then go into standby (monitor) mode without returning acknowledge signal. at the same time, the master also goes into standby status, and communication ends. ? master receive mode the slave outputs the telegraph length bits and parity bit. if even parity is detected by the master, it returns the acknowledge signal. but if odd parity is detected, the master judges that the telegraph length bits have not been correctly received, and goes into the standby status without returning acknowledge signal. then the slave also goes into standby status, and communication ends. (6) data field this field is used by the master to transmit/receive data to/from the slave. this field is consisted of eight data bits with transmitting msb first, parity bit and acknowledge bit. multiaddress communication can only be performed when the master unit transmits data and the acknowledge signal is ignored. the operations for master transmits and receives data are described as follow: ? master transmit mode when the master writes data to a slave, it transmits data bits and parity bit to the slave. then if even parity is detected by the slave and its receive data buffer is not full, the slave returns the acknowledge signal. if odd parity is detected or the receive buffer is full, the slave rejects accepting the corresponding data, and does not return the acknowledge signal. if the acknowledge is not detected by the master, it retransmits the same data until the acknowledge bit is detected or the maximum number of transmit bytes is exceeded. if the parity is even and the acknowledge signal is returned from the slave, the master transmits the next available data if the maximum number of transmit bytes is not exceeded. in multiaddress communication mode, the slave unit does not return the acknowledge signal, and the master transmits data on a 1-byte-by-1-byte basis. ? master receive mode when the master reads data from the slave, the master outputs a synchronous signal corresponding to all the read bits. then the slave outputs the data and parity bit to the iebus in response to the synchronous signal output by the master. after that, the master reads these bits and confirm the parity check. if odd parity is detected or the masters receive buffer is full, it rejects accepting the data and does not return the acknowledge signal. if the maximum number of transmit bytes per frame is not exceeded, the master repeatedly reads the same data. if even parity is detected and the masters receive buffer is not full, the master accepts the data and returns the acknowledge signal. if the maximum number of transmit bytes per frame is not exceeded, the master reads the next data. (7) parity bit the parity bit is used to confirm that the transmit data contains no error. it is appended to master address bits, slave address bits, control bits, telegraph length bits and data bits. the parity is an even parity. if the number of 1 bits in the data is odd, then the parity bit is set to 1. if the number of 1 bits in the data is even, then the parity bit is set to 0. (8) acknowledge bit an acknowledge bit is appended to the following location to confirm whether data has been correctly received in the normal communication mode (communication between one unit and another): ? at the end of slave address field ? at the end of control field ? at the end of telegraph length field 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 169 ? at the end of data field the acknowledge bit is defined as: 0: the transmit data is recognized (ack) 1: the transmit data is not recognized (nak) the acknowledge bit is ignored in multiaddress communication. 1. acknowledge bit at the end of slave field the acknowledge bit at the end of the slave field is treated as nak in any of the following cases, and then transmission is aborted: ? if the parity of the master address bits or slave address bits is not correct ? if a timing error (error in bit format) occurs ? if the specific slave unit does not exist 2. acknowledge bit at the end of the control field the acknowledge bit at the end of the control field is treated as nak in any of the following cases, and then transmission is aborted: ? if the parity of the control bits is not correct ? if bit 3 of the control bits is 1 (write operation) but the slave receive buffer note is full ? if the control bits indicate data read (3h, 7h) but the slave transmit buffer note is empty ? if the slave has been locked, but value of 3h, 6h, 7h, ah, bh, eh or fh in the control bits are requested by another unit other than the one has set locking ? if the control bits indicate reading of a lock address (4h) but the slave has not been locked. ? if a timing error occurs ? if undefined control bit values are set note: refer to slave status (ssr) in (7) 3. acknowledge bit at the end of the telegraph length field the acknowledge bit at the end of the telegraph length field is treated as nak in any of the following cases, and transmission is aborted: ? if the parity of the telegraph length bits is not correct ? if a timing error occurs 4. acknowledge bit at the end of data field the acknowledge bit at the end of the data field is treated as nak in any of the following cases, and then transmission is aborted: ? if the parity of the data bits is not correct note ? if a timing error occurs after the previous acknowledge bit has been transmitted ? if the receive buffer has become full and thus no more data can be accepted note: the same data is retransmitted if the maximum number of transmit data bytes per frame is not exceeded. 13.4 iebus communication protocol 170 chapter 13: ie bus MB90580 series 13.4.7 transmit data the content in data field is controlled by the control bits in control field and is shown below: note1: the direction in which telegraph length bits in the telegraph length field and data in the data field are transferred is changed depending on the value of bit 3 as follows: when bit 3 is 1: transfer from master unit to slave unit when bit 3 is 0: transfer from slave unit to master unit note2: control bits 3h, 6h, ah, bh are used to lock and unlock the unit. when those undefined control bits 1h, 2h, 8h, 9h, ch, dh has been received, the acknowledge bit is not returned. when the slave is locked, it can only execute the following command requesting by other units besides of the master executing the lock command: table 13.4.7a control bits setting bit 3 note 1 bit 2bit 1bit 0 function note 2 0h 0 0 0 0 slave status (ssr) read 1h 0 0 0 1 undefined 2h 0 0 1 0 undefined 3h 0 0 1 1 data read and lock 4h 0 1 0 0 lock address read (lower 8 bits) 5h 0 1 0 1 lock address read (upper 4 bits) 6h0110 slave status (ssr) read and unlock 7h 0 1 1 1 data read 8h 1 0 0 0 undefined 9h 1 0 0 1 undefined ah 1 0 1 0 command write and lock bh 1 0 1 1 data write and lock ch1100undefined dh1101undefined eh1110command write fh1111data write table 13.4.7b the control command that can be executed by a locked slave unit bit 3bit 2bit 1bit 0function 0h 0 0 0 0 slave status (ssr) read 4h 0 1 0 0 lock address read (lower 8 bits) 5h 0 1 0 1 lock address read (upper 4 bits) 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 171 (1) slave status (ssr) read (control bits: 0h, 6h) by reading the slave status, the master can understand why the slave has not returned the acknowledge bit (ack). the slave status is determined in respect to the result of the last communication performed by the slave unit. moreover all slaves can supply the information of slave status as configured below: note1: the slave transmit buffer is the buffer accessed when data is read (control bits: 3h, 7h). this buffer is same as the write data buffer (wdb). note2: the slave receive buffer is the buffer accessed when data is written (control bits: 8h, ah, bh, eh, fh). this buffer is same as the read data buffer (rdb). note3: this bit can be selected by the pcom bit in command register (cmrh). note4: for MB90580 series, 10 is fixed. (2) data/command transfer (control bits: read (3h, 7h), write (ah, bh, eh, fh)) if the control bits indicate data read (3h, 7h), the data in the data buffer of the slave is read by the master. if the control bits indicate data write (bh, fh) or command write (ah, eh), the data received by the slave is processed in accordance with the operation regulation of that slave. note1: the data or command can be selected with the users own decision in the corre- sponding system. note2: the slave is also locked when control bits are 3h, ah and bh. table 13.4.7c meaning of slave status bit value meaning bit 0 note1 0 slave transmit buffer is empty 1 slave transmit buffer is not empty bit 1 note2 0 slave receive buffer is not full 1 slave receive buffer is full bit 2 0 unit is not locked 1 unit is locked bit 3 0 fixed to 0 bit 4 note3 0 slave transmission is stopped 1 slave transmission is enabled bit 5 0 fixed to 0 bit 6 bit 7 00 mode 0 indicates the highest mode that is supported by the unit note 4 01 mode 1 10 mode 2 11 prohibited bit 3 bit 2 bit 4 bit 5 msb lsb bit 1 bit 0 bit 6 bit 7 slave status 13.4 iebus communication protocol 172 chapter 13: ie bus MB90580 series (3) read lock address (control bits: 4h, 5h) when the lock address is read (control bits: 4h, 5h), the address (12-bit) of the master that has issued the lock instruction is configured in 1-byte units as shown below and is read. (4) locking and unlocking the lock function is used to transmit a message over two or more communication frames. the unit that has been locked cannot receive data from any unit other than the one that has locked it. a unit is locked or unlocked as follows: ? locking when the lock command has been executed (control bits: 3h, ah, bh) and the acknowledge bit 0 in the telegraph length field has been transmitted or received, but the number of data bytes specified by the telegraph length bits cannot be transmitted or received successfully within the communication frame, then the slave is locked by the master, and the bit related to locking (bit 2) in the slave status is set. ? unlocking when the lock command (control bits: 3h, ah, bh) or unlock command (control bits: 6h) has been exe- cuted, and the number of data bytes specified by the telegraph length bits can be transmitted or received successful within one communication frame, then the slave is unlocked by the master and the bit related to locking (bit 2) in the slave status is cleared. furthermore, the slave is not locked or unlocked while multiaddress communication is performed. lower 8 bits higher 4 bits undefined control bits: 4h control bits: 5h msb lsb 13.4 iebus communication protocol MB90580 series chapter 13: ie bus 173 13.4.8 bit format the format of the bits constituting an iebus communication frame is shown below: logic 1: voltage difference between inter-bus wires (bus+ and bus-)is below 20 mv (low level) logic 0: voltage difference between inter-bus wires (bus+ and bus-) is above 120 mv (high level) preparation period: first low-level period (logic 1) synchronization period: next high-level period (logic 0) data period: period indicating bit value (logic 1 = low level, logic0 = high level) the length of synchronization period and data period are almost the same. the iebus establishes synchronization for each bit. the specifications of the time of the entire bit and the time of the period assigned to the bit differ depending on the type of the transmit bit, and whether the unit is master or slave. moreover, the specified interval for every period (preparation, synchronization, data) in the communication are detected by both the master and slave. if data cannot be detected within that specified interval, timing error occurs in both master and slave, and then the communication ends and goes into standby mode. preparation period synchronizatio n period data period pause period synchronizatio n period data period logic 1 logic 0 13.5 operation 174 chapter 13: ie bus MB90580 series 13.5 operation 13.5.1 iebus control (1) master transmit the unit is set as master transmit to transmit data to the slave by sending data/command control bits as ah, bh, eh or fh. the sequences for operating in master transmit are described as below: 1. the master address is written in unit address register (mawh, mawl), the slave address is written in slave address register (sawh, sawl), multiaddress bit and control bits are written into multiaddress, control bit set register (dcwr). after that, the command register (cmrh) is set to release communication inhibit mode. 2. when the master has won the arbitration (after the master address field is finished), the state code (0h) indicating start of transmission is set in st3-0 of status register (strl) and transmit interrupt occurs. at this time, the number of transmitted data byte is required to write into telegraph length set register (dewr) and transmit data is set in write data buffer (wdb), unless the wdb is not full. 3. when one byte of data is transmitted, the number of data in wdb is deducted by one. according to the setting of tit1, tit0 in command register (cmrl) that control the interval for writing data in wdb, the transmit interrupt occurs. at that time, the state code equals 1h indicating data transmission and wdb is not full. therefore, data should be written in wdb. 4. if the specified number of data or command has been transmitted correctly, the state code (2h) indicating transmission ends normally is set in st3-0 of status register (strl), the eod bit in strh is set and transmit interrupt occurs. 5. if error occurs during transmission or in multi-frame communication the number of data byte specified in telegraph bit set register (dewr) cannot be transmitted completely, the state code (3h) indicating transmission ends without all data are transmitted is set in st3-0, and transmit interrupt occurs. at this time, the content of communication error can be known by checking the status of tsl, pef, te in status register (strh). when timing error is occurred during the transmission, the data stored in wdb cant be transmitted. if the te bit is cleared and re-transnit sequence is executed, those data left in wdb, excluding the data byte that has timing error will be re-transmit. in order to perform new data transmission, the bit wdbc in cmrl must be written 1 to clear the write data buffer. (2) slave transmit n data transmit this mode is set when the master sends control bits either 3h or 7h to slave and requests it to transmit data back to the master. the sequences for operating in slave data transmit are described as below: 1. after receiving master control code 3h or 7h, the data code (0h) indicating transmit start is set to st3-0 of status register and the transmit interrupt is occurred. at this time, set the telegraph length set register (dewr) with the nunmber of byte of data which are required to be transmitted. the transmit data can be written to wdb, provided that wdb is not full. 2. during the start of telegraph field transmission, the status register bits st3-0 are set to 1h indicating data transmission in progress and transmit interrupt occurs. at that moment, transmit data can be written to the wdb, provided that wdb is not full. 3. when one byte of data is transmitted, the number of data in wdb is deducted by one. according to the setting of tit1, tit0 in command register (cmrl) that control the timing for writing data in wdb, the transmit interrupt occurs. data can be written in wdb if state code is still (1h) and wdb is not full. 4. if the specified number of data or command has been transmitted correctly, the state code (2h) indicating transmission ends normally is set in st3-0 of status register (strl), the eod bit in strh is set and transmit interrupt occurs. 13.5 operation MB90580 series chapter 13: ie bus 175 5. if error occurs during transmission or in multi-frame communication the number of data byte specified in dewr cannot be transmitted completely, the state code (3h) indicating transmission terminated without all data transmitted is set in strl:st3-0. transmit interrupt will occur. at this time, the content of communication error can be known by checking the status of tsl, pef, te in status register (strh). the interval between setting st3-0 and the first data is transmitted out from wdb is shown below: note : 1. number of transmit bytes and transmit data can be set during the interrupt generated after the receiving of control bits. 2. as the time between the wdb empty interrupt and the next telegraph bit transmit interrupt is very short, thus it is recommended to take the following precautions when the first transmit data is required to write into wdb. ? only write data to wdb after the wdb empty confirmation. ? in case of setting the transmit data byte count, it is required to set the value within the time listed in table 13.5.1a. the default value of the transmit data byte count will transmit 256bytes. ? if at least 1 byte of data is not set within the time listed in below after the transmit interrupt, wdb will be detected as empty. error will be occurred after the transmission of telegraph field and the communication will be terminated. n slave status, lock address transmit when the control bits 0h, 4h, 5h, 6h has been received from the master, the slave status, lock address are automatically transmitted to the master. in this way, there is no need to write data into wdb, but it is required to set 1h to the telegraph bit setting register. (3) master receive the unit is set as master receive for getting data, slave status and lock address from the slave by first sending control bits 0h, 3h, 4h, 5h, 6h or 7h. the sequences for operating as master receive are described as below: 1. when the slave receives the control bits, it transmits the telegraph length bit. then after the master receives these telegraph length bits and returns the acknowledge bit, the number of received data byte is written into the telegraph length read register (derr). at this moment, no interrupt occurs. 2. after the acknowledge bit in telegraph length field is sent by the master, data reception will be started. and for each received data byte, the master stores it in the read data buffer (rdb). 3. after eight bytes of data are received, the state code (5h) is set in st3-0 of status register (strl), receive interrupt occurs. 4. when the last byte of data is received and stored in rdb within one communication frame, the state code (5h) is set in st3-0 and receive interrupt occurs. this interrupt will be generated even thought rdb is not full. 5. if error is occurred during reception, or the maximium number of data byte has been received in one communication frame, the master cannot received the number of data byte specified in telegraph field and communication is terminated. the state code (7h) indicating master receive ends without all data are received is set in st3-0, and receive interrupt occurs. table 13.5.1a time required to write transmit data to wdb after transmit interrupt has occurred mode time ( m s) number of cycles 0 approx. 158 approx. 1900 1 approx. 40 approx. 480 2 approx. 29 approx. 350 13.5 operation 176 chapter 13: ie bus MB90580 series (4) slave receive this mode is set when the slave unit receive control bits ah, bh, eh or fh from the master. the sequences for operating as slave receive are described as below: 1. after the slave returns the acknowledge bit in telegraph length field, the number of receive data byte is written in the telegraph length read register (derr). at this moment, no interrupt occurs. 2. following the telegraph length field is the data field, the master starts transmitting data and each received data byte is stored in the read data buffer (rdb). 3. after eight bytes of data are received, the state code (9h) indicating slave receive buffer full is set in st3-0 of status register (strl), and receive interrupt occurs. if the receive interrupt occurs, the rdb can be read after the confirmation of buffer not empty. 4. when the last byte of data in one communication frame is received and stored in rdb, the state code (ah) indicating slave receive ends normally is set in st3-0 and receive interrupt occurs. this interrupt will occur even thought the buffer is not full. 5. if error is occurred during reception or the maximium number of data byte has been re3ceived in one commmunication frame, the slave cannot receive the number pf data byte specified in telegraph field and communication is terminated.. the state code (bh) indicating slave receive ends without all data are received is set in st3-0, and receive interrupt occurs. (5) multiaddress receive 1. after the slave has received the telegraph length field, the number of receive data byte is written in the telegraph length read register (derr). at this moment, no interrupt occurs. 2. after the telegraph lenght field is received, each correctly received data byte is stored in the read data buffer (rdb). 3. after eight bytes of data are received, the state code (dh) indicating multiaddress receive buffer full is set in st3-0 of status register (strl), and receive interrupt occurs. if the receive interrupt occurs, the rdb can be read after the confirmation of buffer not empty. 4. when the last byte of data in one communication frame is received and stored in rdb, the state code (eh) indicating multiaddress receive ends normally is set in st3-0 and receive interrupt occurs. this interrupt will occur even thought the buffer is not full. 5. if error is occurred during reception or the maximium number of data byte has been received in one communication frame, the slave cannot receive the number of data byte specified in telegraph field and communication is terminated. the state code (fh) indicating multiaddress receive ends without all data are received is set in st3-0, and receive interrupt occurs. for detail description on st3-0, please refer to table 13.5.2a. 13.5 operation MB90580 series chapter 13: ie bus 177 13.5.2 communication status in the status register, there are four bits st3-0 indicating the status code. after the status code has been set, interrupt request is generated. during the interrupt routine, the communication status can be investigated by reading the status register. but at the beginning of master, slave and multiaddress receive, no interrupt will be generated (1) master, slave data transmit (transmit interrupt occurs) when the unit won the arbitration in multiaddress or master address field, it becomes master unit. then data/command is transmitted to or data is received from the slave, and the status code st3-0 is set and shown as below: (2) master receive (receive interrupt occurs) when the unit won the arbitration in multiaddress or master address field, it becomes master unit. then data, status or log address are received from slave unit, and the status code st3-0 is set and shown as below: table 13.5.2a meaning of status code st3-0 for master, slave transmit code name code st3-0 content transmit starts 0000 indicates start of master/slave transmission. 1) master transmit indicates the master address field in communication frame has been transmitted, and the unit has won in arbitration as the master. 2) slave transmit indicates that the unit has received control bits 0h, 3h, 4h, 5h, 6h, 7h from the master that requests data transmission, and slave data transmission is started. transmit data 0001 indicates that data is transmitting by master unit or slave unit. this control code will be set after the starting of telegraph length field transmission. transmit ends normally 0010 indicates that the number of data transmit specified by telegraph length field has been completed within one communication frame ends without all data being transmitted 0011 indicates that the communication has ended without transmitting the number of data specified by telegraph length field in one communication frame. table 13.5.2b meaning of status code st3-0 for master receive code name code st3-0 content master receive starts 0100 indicates that the master has received the telegraph field correctly from the slave and master reception is started but receive interrupt does not occur at this moment. master receive data full 0101 indicates that the receive data buffer rdb for master reception is full (eight byte of data has been received), and the host controller is requested to read data from the rdb. master receive ends normally 0110 indicates the number of data specified by the telegraph field has been received within one communication frame. ends without all data being received 0111 indicates that the communication has ended without receiving the number of data specified by telegraph length field in one communication frame. 13.5 operation 178 chapter 13: ie bus MB90580 series (3) slave receive (receive interrupt occurs) when data/command is received from the master unit, the status code st3-0 is set and shown as below: (4) multiaddress receive (receive interrupt occurs) when the data/command in multiaddress communication are received from the slave unit, the status code st3-0 is set and shown as below: table 13.5.2c meaning of status code st3-0 for slave receive code name code st3-0 content slave receive starts 1000 indicates that the slave unit has received the telegraph field correctly from master unit and slave reception is started but receive interrupt does not occur at this moment. slave receive data full 1001 indicates that the receive data buffer rdb for slave reception is full (eight byte of data has been received), and the host controller is requested to read data from the rdb. slave receive ends normally 1010 indicates the number of data specified by the telegraph field has been received within one communication frame. ends without all data being received 1011 indicates that the communication has ended without receiving the num- ber of data specified by telegraph length field in one communication frame. table 13.5.2d meaning of status code st3-0 for multiaddress receive code name code st3-0 content multiaddress receive starts 1100 indicates that the slave unit has received the telegraph field correctly from master unit and multiaddress reception is started but receive interrupt does not occur at this moment. multiaddress receive data full 1101 indicates that the receive data buffer rdb for slave reception is full (eight byte of data has been received), and the host controller is requested to read data from the rdb. multiaddress receive ends normally 1110 indicates the number of data specified by the telegraph field has been received within one communication frame. ends without all data being received 1111 indicates that the communication has ended without receiving the num- ber of data specified by telegraph length field in one communication frame. 13.5 operation MB90580 series chapter 13: ie bus 179 13.5.3 program flow example for iebus controller (1) main routine (2) interrupt routine this routine is executed when start of transmission or end of reception. in interrupt routine, the status code (st3-0) in status register strl is read, then the transmit data can be written or receive data can be read. begin iebus initial setup enable iebus controller iebus controller operates end begin read status register categorize the status code master master transmit routine note1 slave transmit routine note2 master receive routine note3 slave receive routine multiaddress receive routine reti end upper 2 bits of st3- 00 01 10 11 yn note1: refer to master transmit routine note2: refer to slave transmit routine note3: refer to master receive routine interrupt enable 13.5 operation 180 chapter 13: ie bus MB90580 series (3) iebus initial setup the initial setup sequence includes setting its unit address, the command register and releasing the communication inhibit state. if the unit is not set as master, there is no need to set the slave address in slave address register. in converse, if the unit is set as master, there is no need to set the mutiaddress byte and control byte. begin set unit address (mawh, mawl) set slave address (sawh, sawl) set multiaddress and control bits (dcwr) set as master set command register (cmrh, cmrl) release communication inhibit state end y n when the unit is set as master, the unit address becomes master address. when the unit is set as slave, the unit address is used to compared with that in slave address field. for example selecting the communication mode in command register cmrh, cmrl the bit pcom in command register cmrh is set to 1. data transmit y n enable transmit during slave receive, .gotm and gots are not set gots bit to 1 when gotm bit is 1/ note: it can be executed by write operation of command register. 13.5 operation MB90580 series chapter 13: ie bus 181 (4) master transmit routine after the communication inhibit state is released, the unit won the arbitration and acts as master. then master transmit routine is used to transmit data to the slave. this routine is executed inside interrupt routine with st3-0 bits (upper 2 bits are 00) in status register indicating the status as master transmit has been set. begin status register read set multiaddress, control bits sand telegraph length bits st3-0 = 3h? end n y transmission ends without all data being transmitted st3-0 = 0h? n n = 0? n y wdbf = 1? n y y wdb write n = n-1 st3-0 = 2h? n y done by setup master transmit data note1 note2 note2 note1: the reason for the abnormal termination of transmission can be known by reading the te, pef and ack bits of status register. the remaining data that cant be transmitted will be sent out when gotm bit in command reg- ister cmrh is written 1 again. in order to stop the master transmit and clear the wdb, the bit wdbc in cmrl is written 1. note2: please do not wrtie wdb when wdbf=1 note3: n is the number of data byte for master transmit 13.5 operation 182 chapter 13: ie bus MB90580 series (5) slave transmit routine after the slave receives the control bits and is set as slave transmit, this routine is used to transmit data to the master. this routine is executed inside interrupt routine with st3-0 bits (upper 2 bits are 00) in status register indicating the status as slave transmit has been set. begin status register read set telegraph length got = 1 st3-0 = 3h? end n y transmission ends without all data being transmitted st3-0 = 0h? n n = 0? n y wdbf = 1? n y y wdb write got = 1 n = n-1 st3-0 = 2h? n y done by hardware setup slave transmit data data transmit data transmit note1 note2 note2 note1: the reason for the abnormal termination of transmission can be known by reading the te, pef and ack bits of status register. the remaining data that cant be transmitted will be sent out when gots bit in command register cmrh is written 1 again. in order clear the wdb, the bit wdbc in cmrl is written 1. note2: please do not wrtie wdb when wdbf=1 note3: n is the number of data byte for slave transmit 13.5 operation MB90580 series chapter 13: ie bus 183 (6) master receive routine after the master transmit the control bits, this routine is used for the master to receive data, slave address or log address from the slave. this routine is consisted of four parts depending on the content of st3-0. 1. start of master reception (st3-0 is 4h) when the master receive the telegraph length field from the slave correctly, the status code 4h is set and the master reception starts. however, interrupt will not occur at that time.. note1: the status register need not be read because each registers are set. however, it is required to take care the timing of setting the registers. before updating the register contents, read the registers first. note2: n is the number of data byte for master receive. 2. master received data read request (st3-0 is 5h) note1: do not read rdb when rdbe=1. note2: n is the number of data byte for master receive. begin read multiaddress, control bits and telegraph length bits n number of master receive data byte end read out multiaddress, control bits and master receive byte number done by hardware note2 note1 begin i = 8 i i - 1 rdb read end master receive buffer size done by hardware done by hardware n n - 1 rdbe = 1? n y done by hardware note1 note2 13.5 operation 184 chapter 13: ie bus MB90580 series 3. master receive ends normally (st3-0 is 6h) begin rdb read end n n - 1 rdbe = 1? y n done by hardware read multiaddress, control bits and telegraph length bits read out multiaddress, control bits and master receive byte number n number of master receive data byte done by hardware done by hardware read out master receive data note1 note2 note1: it is not required to read the status as these data are stored in different regis- ters. as the data will be updated, read the register before the next communica- tion frame. note2: do not read rdb when rdbe = 1. 13.5 operation MB90580 series chapter 13: ie bus 185 4. master reception ends without all data being received (st3-0 is 7h) the routine for slave receive and multiaddress receive is the same as that of master receive but the status code is different. please refer to section 13.5.2 for the status code of slave receive and multiaddress receive. begin strh/l read end rdbe = 1? n y read multiaddress, control bits and telegraph length bits read out multiaddress, control bits and master receive byte number n number of master receive data byte done by hardware read rdb note2 note1: it is not required to read the status as these data are stored in different registers. as the data will be updated, read the register before the next communication frame. note2: do not read rdb when rdbe = 1. note1 read out master received data 13.5 operation 186 chapter 13: ie bus MB90580 series 13.5.4 timing diagram of multiple frame transmission 1. when setting 1 on wdbc (master side of master transmission) figure 13.5.4a when setting 1 on wdbc (master side of master transmission) frist frame com second frame datan-3(04h) note : n = n bytes transmission. the number inside () is the transmission data. write until wdb becomes full wdbf wdb is empty as wdbc=1 wedbf=0 due to1 byte transmission wdbe derr read can read the rest of the transmission byte transmission data left is 0 wdbc write the transmission data 8 bytes n deer dewr write write derr value transmit the rest of 2 bytes 02h dewr wdb transmit the data newly set trans. buffer n wdb write multi-add start master- add feh 07h, 06h, 05h, 04h, 04h, 03h, 02h, 01h, 00h ffh, feh, fdh, fch, fbh, fah, f9h 02h 00h 03h feh datan-2(03h) slave-add control telegraph bytes datan-1(ffh) datan(feh) 13.5 operation MB90580 series chapter 13: ie bus 187 2. when setting 0 on wdbc (master side of master transmission) figure 13.5.4b when setting 0 on wdbc (master side of master transmission) frist frame com second frame note : n = n bytes transmission. the figure inside ()is the transmission data. write until wdb becomes full wdbf wedbf=0 due to1 byte transmission wdbe derr read wdbc as data is left from 3 bytes before, write transmission data 5 bytes n deer dewr write write derr value transmit the rest of 2 bytes 02h dewr wdb transmit the previous frame's data trans. buffer 02h n wdb write 01h 07h, 06h, 05h, 04h, 04h, 03h, 02h, 01h, 00h ffh, feh, fdh, fch, fbh 02h 00h 03h datan-3(04h) multi-add start master- add datan-2(03h) slave-add control telegraph bytes datan-1(02h) datan(01h) can read the rest of the transmission bytes transmission data left is 0 13.5 operation 188 chapter 13: ie bus MB90580 series 13.5.5 timing diaram of transmission data when an error is generated 1. the following is an example when the master transmission, an error is generated at the second byte data on the slave side. nak is received by the master. the following data is transmitted at the second frame. figure 13.5.5a error happened on the slave side when master transmission re-transmit until the figure becomes the maximum transmission byte header data filed 13.5 operation MB90580 series chapter 13: ie bus 189 2. the following is an example when the master transmission, an error is generated at the second byte data on the master side. the following data is transmitted at the second frame. figure 13.5.5b error happened on the master side when master transmission slave reception movements until the figure becomes the maximum transmission byte header data filed chapter 14: 8/16-bit ppg 14.1 outline the 8/16-bit ppg timer is an 8-bit reload timer module, and outputs ppg by control pulse output according to timer operation. the hardware includes two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the following functions are implemented: ? 8-bit ppg output 2-ch independent operation mode this is a mode for operating independent 2-ch 8-bit ppg timer, in which ppg0 and ppg1 pins corre- spond to outputs from ppg0 and ppg1 respectively. ? 16-bit ppg output operation mode in this mode, ppg0 and ppg1 are combined to be operated as a 1-ch 8/16-bit ppg timer operating as a 16-bit timer. because prg0 and prg1 outputs are reversed by an underflow from prg1 outputting the same output pulses from prg0 and prg1 pins. ? 8 + 8 bit ppg output operation mode in this mode, ppg0 is operated as an 8-bit pre-scaler, in which an underflow output of ppg0 is used as a clock source for ppg1. a toggle output of ppg0 and ppg output of ppg1 are output from ppg0 and ppg1 respectively. ? ppg output operation the 8/16-bit ppg timer can output pulse waveforms with variable period and duty ratio. also, it can be used as d/a converter in conjunction with an external circuit. 14.2 block diagram 192 chapter 14: 8/16-bit ppg MB90580 series 14.2 block diagram figure 14.2a 8-bit ppg ch0 block diagram ppg0 pen0 irq s r q prll0 prlbh0 prlh0 pie0 puf0 ppgc0 l data bus h data bus (operation mode control) ppg0 output enable peripheral clock 16-division peripheral clock 8-division peripheral clock 4-division peripheral clock 2-division peripheral clock ppg0 output latch invert clear time base counter output 512-division of main clock count clock pcnt reload ch1-borrow l/h selection l/h selector selection (down counter) a/d converter 14.2 block diagram MB90580 series chapter 14: 8/16-bit ppg 193 figure 14.2b 8-bit ppg ch1 block diagram ppg1 pen1 s r q irq pie puf prll1 prlbh1 prlh1 ppgc1 peripheral clock peripheral clock 16-division peripheral clock 8-division peripheral clock 2-division peripheral clock 4-division ppg1 output latch invert clear time base counter output 512-division of main clock ch0 borrow count clock pcnt selection (down counter) reload l/h selection l/h selector l data bus h data bus (operation mode control) uart ppg0 output enable 14.3 registers and register details 194 chapter 14: 8/16-bit ppg MB90580 series 14.3 registers and register details figure 14.3a registers of 8/16-bit ppg address: ch0 000040h ch1 000042h (r/w) (r/w) (x) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) prll prlh bit no. 76 54 3 2 1 0 bit no. 15 14 13 12 11 10 9 8 (r/w) (x) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) address: ch0 000041h ch1 000043h address: ch0 1 0046h , bit no. 76 5 432 10 ppgoe pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 reserved reserved bit no. 15 14 13 12 11 10 9 8 bit no. 76 54 3 2 1 0 address: ch0 000045h address: ch0 000044h (-) (0) (x) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (-) (1) (r/w) pen1 pe10 pie1 puf1 md1 md0 pen0 pe00 pie0 puf0 (-) (0) (x) (r/w) (0) (r/w) (0) (r/w) (0) (-) (x) (-) (x) (-) (1) (r/w) ppgc1 ppgc0 ppg0 operation mode control register read/write initial value read/write initial value read/write initial value read/write initial value read/write initial value reserved reserved ppg1 operation mode control register ppg0,1 output control register reload register h reload register l (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) 14.3 registers and register details MB90580 series chapter 14: 8/16-bit ppg 195 14.3.1 ppg0 operation mode control register (ppgc0) ppgc0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. [bit 7] pen0 (ppg enable): operation enable bit this bit selects the ppg operation mode as described below. setting this bit to 1 makes the ppg start counting. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 5] pe00 (ppg output enable 0): ppg0 pin output enable bit this bit controls the ppg0 pulse output external pin as described below. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 4] pie0 (ppg interrupt enable): ppg interrupt enable bit this bit controls ppg interrupt as described below. while '1' is written to this bit, an interrupt request is issued as soon as '1' is written to puf0. no inter- rupt request is issued while this bit is set to '0.' this bit is initialized to '0' upon a reset. this bit is readable and writable. note: pie0 is assigned the same interrupt vector number as that of 16-bit reload timer. when using ei 2 os in 16-bit reload timer, write '0' to pie0. [bit 3] puf0 (ppg underflow flag): ppg counter underflow bit bit no. 76 54 3 2 1 0 address: ch0 000044h pen0 pe00 pie0 puf0 (-) (0) (x) (r/w) (0) (r/w) (0) (r/w) (0) (-) (x) (-) (x) (-) (1) (r/w) ppgc0 ppg0 operation mode control register read/write initial value reserved operation 0 stop ('l' level output maintained) [initial value] 1 ppg operation enabled pen0 operation 0 general-purpose port pin (pulse output disabled) [initial value] 1 ppg0 = pulse output pin (pulse output enabled) pe00 operation 0 interrupt disabled [initial value] 1 interrupt enabled pie0 14.3 registers and register details 196 chapter 14: 8/16-bit ppg MB90580 series this bit controls the ppg counter underflow as described below. in 8-bit ppg 2ch mode or 8-bit prescaler + 8-bit ppg mode, '1' is written to this bit when an underflow occurs as a result of the ch0 counter value becoming between 00h and ffh. in 16-bit ppg 1ch mode, '1' is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming between 0000h and ffffh. to set this bit to '0,' write '0.' writing '1' to this bit is invalid. upon a read operation during a read-modify-write instruction, '1' is read. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 0] this is a reserved bit. when setting ppgc0, always set this bit to 1. operation 0 ppg counter underflow is not detected [initial value] 1 ppg counter underflow is detected puf0 14.3 registers and register details MB90580 series chapter 14: 8/16-bit ppg 197 14.3.2 ppg1 operation mode control register (ppgc1) ppgc0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers. [bit 15] pen1 (ppg enable): operation enable bit this bit selects the ppg operation mode as described below. setting this bit to 1 makes the pwm start counting. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 13] pe10 (ppg output enable 1): ppg1 pin output enable bit this bit controls the ppg1 pulse output external pin as described below. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 12] pie1 (ppg interrupt enable): ppg interrupt enable bit this bit controls ppg interrupt as described below. while '1' is set in this bit, an interrupt request is issued as soon as '1' is written to puf1. no interrupt request is issued while this bit is set to '0.' this bit is initialized to '0' upon a reset. this bit is readable and writable. note: pie1 is assigned the same interrupt vector number as that of uart 0 transmission complete. when using ei 2 os in uart 0 transmissioin complete, write '0' to pie1. bit no. 15 14 13 12 11 10 9 8 address: ch0 000045h (-) (0) (x) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (r/w) (0) (-) (1) (r/w) pen1 pe10 pie1 puf1 md1 md0 ppgc1 read/write initial value reserved ppg1 operation mode control register operation 0 stop ('l' level output maintained) [initial value] 1 ppg operation enabled pen1 operation 0 general-purpose port pin (pulse output disabled) [initial value] 1 ppg1 = pulse output pin (pulse output enabled) pe10 operation 0 interrupt disabled [initial value] 1 interrupt enabled pie1 14.3 registers and register details 198 chapter 14: 8/16-bit ppg MB90580 series [bit 11] puf1 (ppg underflow flag): ppg counter underflow bit this bit controls the ppg counter underflow as described below. in 8-bit ppg 2ch mode or 8-bit prescaler + 8-bit ppg mode, '1' is written to this bit when an underflow occurs as a result of the ch1 counter value becoming between 00h and ffh. in 16-bit ppg 1ch mode, '1' is written to this bit when an underflow occurs as a result of the ch1/ch0 counter value becoming between 0000h and ffffh. to set '0' in this bit, write '0.' writing '1' to this bit is invalid. upon a read operation during a read-modify-write instruction, '1' is read. this bit is initialized to '0' upon a reset. this bit is readable and writable. [bit 10, 9] md2, 1 (ppg count mode): operation mode selection bit this bit selects the ppg timer operation mode as described below. this bit is initialized to '00' upon a reset. this bit is readable and writable. note: do not set '10' in this bit. note: to write '01' to this bit, ensure that '01' is not written to the pen0 bit of ppgc0 or pen1 bit of ppgc1. write '11' or '00' in both the pen0 and pen1 bits simultaneously. note: to write '11' to this bit, update ppgc0 and ppgc1 by word transfer and write '11' or '00' to both the pen0 and pen1 bits simultaneously. [bit 8] this is a reserved bit. when setting ppgc0, always write 1 to this bit. operation 0 ppg counter underflow is not detected [initial value] 1 ppg counter underflow is detected puf1 0 0 8-bit ppg 2ch independent mode 0 1 8-bit prescaler + 8-bit ppg 1ch mode 1 0 reserved (setting inhibited) 1 1 16-bit ppg 1ch mode operation mode md1 md0 14.3 registers and register details MB90580 series chapter 14: 8/16-bit ppg 199 14.3.3 ppg0, 1 output pin control register (ppgoe) this is an 8-bit control register that controls the pin output of this block. [bits 7 to 5) pcs2 to 0 (ppg count select): count clock selection bit these bits select the channel 1 down counter operation clock as described below. this bit is initialized to '000' upon a reset. this bit is readable and writable. note: in 8-bit prescaler + 8-bit ppg mode or in 16-bit ppg mode, ch1 ppg operates in response to a counter clock from ch0. therefore, the pcs1 bit is invalid. [bits 4 to 2] pcm2 to 0 (ppg count mode): count clock selection bit these bits select the channel 0 down counter operation clock as described below. this bit is initialized to '000' upon a reset. this bit is readable and writable. address: ch0 1 0046h , bit no. 76 5 432 10 ppgoe pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 reserved reserved read/write initial value ppg0,1 output control register (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) 0 0 0 peripheral clock (62.5-ns machine clock, 16 mhz) 0 0 1 peripheral clock/2 (125-ns machine clock, 16 mhz) 0 1 0 peripheral clock/4 (250-ns machine clock, 16 mhz) 0 1 1 peripheral clock/8 (500-ms machine clock, 16 mhz) 1 0 0 peripheral clock/16 (1-ms machine clock, 16 mhz) 1 1 1 clock input from time base counter (128-ms, 4-mhz source operation mode pcs2 pcs1 pcs0 0 0 0 peripheral clock (62.5-ns machine clock, 16 mhz) 0 0 1 peripheral clock/2 (125-ns machine clock, 16 mhz) 0 1 0 peripheral clock/4 (250-ns machine clock, 16 mhz) 0 1 1 peripheral clock/8 (500-ms machine clock, 16 mhz) 1 0 0 peripheral clock/16 (1-ms machine clock, 16 mhz) 1 1 1 clock input from time base counter (128-ms, 4-mhz source operation mode pcm2 pcm1 pcm0 14.3 registers and register details 200 chapter 14: 8/16-bit ppg MB90580 series 14.3.4 reload register (prll/prlh ) these are 8-bit registers that hold the reload values for the pcnt down counter. their roles are described below. these registers are readable and writable. note: in 8-bit prescaler + 8-bit ppg mode, setting different values in prll and prlh of ch1 may cause the ppg waveform of ch1 to vary in each cycle. write the same value to prll and prlh of ch0. address: ch0 000040h ch1 000042h (r/w) (r/w) (x) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) prll prlh bit no. 76 54 3 2 1 0 bit no. 15 14 13 12 11 10 9 8 (r/w) (x) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) (x) (r/w) address: ch0 000041h ch1 000043h read/write initial value read/write initial value reload register h reload register l function prll holds the l side reload value. prlh holds the h side reload value. register name 14.4 operations MB90580 series chapter 14: 8/16-bit ppg 201 14.4 operations this block has two channels of 8-bit ppg units. these two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit ppg mode, and single-channel 16-bit ppg mode. each of the 8-bit ppg units has two eight-bit reload registers. one reload register is for the l side (prll) and the other is for the h side (prlh). the values stored in these registers are reloaded into the 8-bit down counter (pcnt), from the l side and h side in turn. thus, the values are decremented for each count clock, and the pin output (ppg) value is inverted upon a reload caused by a counter borrow. this operation results in l-wide or h-wide pulse outputs, corresponding to the reload register value. the operation is started and resumed by writing data in the corresponding register bit. the table below lists the relationship between the reload operation and pulse outputs. when 1 is set in bit 4 (pie0) of ppgc0 or in bit 12 (pie1) of ppgc1, an interrupt request is output upon a borrow from 00 to ff (from 0000 to ffff in 16-bit ppg mode) of each counter. (1) operation mode this block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit ppg mode, and single-channel 16-bit ppg mode. in independent two-channel mode, the two channels of 8-bit ppg units operate independently. the ppg0 pin is connected to the ch0 ppg output, while the ppg1 pin is connected to the ch1 ppg output. in 8-bit prescaler + 8-bit ppg mode, ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0. thus, 8-bit ppg waveforms can be output at any cycles. the ppg0 is connected to the ch0 prescaler output, while the ppg1 pin is connected to the ch1 ppg output. in 16-bit ppg 1ch mode, ch0 and ch1 are connected and used as a single 16-bit ppg. the ppg0 and ppg1 pins are connected to the 16-bit ppg output. table 14.4a reload operation and pulse output reload operation pin output change prlh pcnt ppg0x/1x [0 1] rise prll pcnt ppp0x/1x [1 0] fall 14.4 operations 202 chapter 14: 8/16-bit ppg MB90580 series (2) ppg output operation in this block, the ch0 ppg is activated to start counting when '1' is written to bit 7 (pen0) of the ppgc0 (pwm operation mode control) register. similarly, the ch1 ppg is activated to start counting when '1' is written to bit 15 (pen1) of the ppgc1 register. once the operation has started, counting is terminated by writing '0' to bit 7 (pen0) of ppgc0 or in bit 15 (pen1) of ppgc1. once the counting is terminated, the pulse output is maintained at the l level. in 8-bit prescaler + 8-bit ppg mode, do not set ch1 to be in operation while ch0 operation is stopped. in 16-bit ppg mode, ensure that bit 7 (pen0) of ppgc0 register and bit 15 (pen1) of ppgc1 register are started or stopped simultaneously. the figure below is a diagram of ppg output operation. during ppg operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the h-level period of the pulse wave to the l-level period). ppg continues operation until stop is specified explicitly. figure 14.4a ppg output operation, output waveform (3) reload value and pulse width the width of the output pulse is determined by adding 1 to the reload register value and multiplying it by the count clock cycle. note that when the reload register value is 00 h during 8-bit ppg operation or 0000 h during 16-bit ppg operation, the pulse width is equivalent to one count clock cycle. in addition, note that when the reload register value is ff h during 8-ppg operation, the pulse width is equivalent to 256 count clock cycles. when the reload register value is ffff h during 16-bit ppg operation, the pulse width is equivalent to 65536 count clock cycles. an example of pulse width calculation is given below. pen ppg (start) t x (l+1) t x (h+1) l : prll value h : prlh value t : input from peripheral clock ( ? , ? /4, ? /16) or timer base counter (depending on the clock selection by ppgc) output pin 2.starts operation based on pen (from lside). l:prll value h: value t : input clock cycle ph : high pulse width pl : low pulse width p1=t x (l+1) ph=t x (h+1) 14.4 operations MB90580 series chapter 14: 8/16-bit ppg 203 (4) count clock selection the count clock used for the operation of this block is supplied from a peripheral clock or time base counter. the count clock can be selected from six types. select ch0 clock at bit 4 to 2 (pcm2 to 0) of the ppgoe register, and ch1 clock at bit 7 to s (pcs2 to 0) of the ppgoe register. the clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock from a time base counter. in 8-bit prescaler + 8-bit ppg mode or 16-bit ppg mode, however, the value in bit 14 (pcs1) of the ppgc1 register is invalid. the register is invalid because ch1 ppg receives a count clock from ch0. when the time base counter input is used, the first count cycle after a trigger or a stop may be shifted. the cycle may also be shifted if the time base counter is cleared during operation of this module. in 8-bit prescaler + 8-bit ppg mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted. (5) pulse pin output control the pulses generated by this module can be output from external pins ppg0 and ppg1. to output the pulses from an external pin, write '1' to the bit corresponding to each pin. use bit 5 (pe0) of the ppgc0 register for the ppg0 pin, bit 13 (pe1) of the ppgc1 register for the ppg1 pin. when '0' is written to these bits (default), the pulses are not output from the corresponding external pins; the pins work as general-purpose ports. in 16-bit ppg mode, the same waveform is output from ppg0 and ppg1. thus, the same output can be obtained by enabling any external pin. in 8-bit prescaler + 8-bit ppg mode, the 8-bit prescaler toggle output waveform is output from ppg0, while the 8-bit ppg waveform is output from ppg1. the figure below is a diagram of output waveforms in this mode. figure 14.4b 8+8 ppg output operation waveform l0 : ch0 prll value and ch0 prlh value l1 : ch1 prll value h1 : ch1 prlh value t : input clock cycle ph0 : ppg0 high pulse width pl0 : ppg0 low pulse width ph1 : ppg1 high pulse width pl1 : ppg1 low pulse width ph0 pl0 ph1 pl1 ppg0 ppg 1 pl0 = t x (l0+1) ph0 = t x (l0+1) pl1 = t x (l0+1) x (ll+1) ph1 = t x (l0+1) x (hl+1) note : set the same value in ch0 prll and ch0 prlh. 14.4 operations 204 chapter 14: 8/16-bit ppg MB90580 series (6) interrupts for this module, an interrupt becomes active when the reload value is counted out and a borrow occurs. in 8-bit ppg 2ch mode or 8-bit prescaler + 8-bit ppg mode, an interrupt is requested by a borrow in each counter. in 16-bit ppg mode, pug0 and puf1 are simultaneously set by a borrow in the 16-bit counter. therefore, enable only pie0 or pie1 to unify the interrupt causes. in addition, simultaneously clear the interrupt causes for puf0 and puf1. (7) default values of hardware components the hardware components of this block are initialized to the following values when reset: 14.4 operations MB90580 series chapter 14: 8/16-bit ppg 205 (8) reload register write timing in a mode other than 16-bit ppg mode, it is recommended to use a word transfer instruction to write data in reload registers prll and prlh. if two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing. figure 14.4c write timing chart assume that prll is updated from a to c before point ? in the time chart above, and prlh is updated from b to d after point ? . since the prl values at point ? are prll=c and prlh=b, a pulse of l side count value c and h side count value b is output only once. similarly, to write data in prl of ch0 and ch1 in 16-bit ppg mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. in this mode, the data is only temporarily written to ch0 prl. then, the data is actually written into ch0 prl when the ch1 prl is written to. in a mode other than 16-bit ppg mode, ch0 and ch1 prl are written independently. figure 14.4d prl write operation block diagram ppg0 bbcc a a d d cb ? ch0 prl write data ch0 write in a mode other temporary latch transferred in synchronization ch1 prl write data ch0 prl ch1 write ch1 prl than 16-bit ppg mode with ch1 write in 16-bit ppg mode chapter 15: 16-bit reload timer (with event count function) 15.1 outline the 16-bit reload timer 1 consists of a 16-bit down-counter, a 16-bit reload register, one input pin (tin) and one output pin (tout), and a control register. it has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used. for this timer, an underflow is defined as the timing of transition from the counter value of 0000 h to ffff h . according to this definition, an underflow occurs after [re-load register setting value + 1] counts. in operating the counter, the re-load mode for repeating counting operation after re-loading a counter value after an underflow or the one-shot mode for stopping the counting operation after an underflow can be selectively used. because the timer can generate an interrupt upon an underflow, the timer conforms to the extended intelli- gent i/o service (ei 2 os). the output pin (tout) outputs a toggle output waveform in reload mode or a square waveform during counting in one-shot mode. the input pin (tin) functions as the event input in event count mode, or as the trigger input or gate input in internal clock mode. 15.2 block diagram 208 chapter 15: 16-bit reload timer (with event count function) MB90580 series 15.2 block diagram figure 15.2a block diagram of 16-bit reload timer 16 8 16 2 2 3 3 exck gate csl1 csl0 in ctl mod2 mod1 mod0 uf f 2 5 out ctl. reld oute outl inte uf cnte trg irq i 2 osclr 16-bit reload register 16-bit down-counter reload clock selector re-trigger prescaler clear peripheral clock clear port (tin) port (tout) serial baud rate (ch0) a/dc (ch1) output enable f 2 mc-16lx bus f 2 3 f 2 1 15.3 registers and register details MB90580 series chapter 15: 16-bit reload timer (with event count function) 209 15.3 registers and register details figure 15.3a registers of 16-bit reload timer 15 14 13 12 11 10 9 8 csl1 csl0 mod2 mod1 y t (r/w)(r/w)(r/w)(r/w) (0) (0) (0) (0) bit number read/write initial value timer control status register (upper) 7 6 5 4 3 2 1 0 mod0 oute outl reld inte uf cnte trg (r/w)(r/w)(r/w)(r/w)(r/w)(r/w)(r/w)(r/w) (0) (0) (0) (0) (0) (0) (0) (0) tmcsr0-2 y t bit number timer control status register (lower) read/write initial value 15 14 13 12 11 10 9 8 ch1 00003f h y t (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) address: ch0 00003b h read/write initial value 16-bit timer register (upper)/ 16-bit reload register (upper) 7 6 5 4 3 2 1 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) tmr0-2/ ch1 00003e h y t tmrlr0-2 bit number bit number 16-bit timer register (lower)/ address: ch0 00003a h 16-bit reload register (lower) read/write initial value address: ch0 000048 h ch1 00004c h ch2 000050 h address: ch0 00004b h ch1 00004f h ch2 000053 address: ch0 00004a h ch1 00004e h ch2 000052 h address: ch0 000049 h ch1 00004d h ch2 000051 h tmr0-2/ tmrlr0-2 tmcsr0-2 (high) (low) (low) (high) 15.3 registers and register details 210 chapter 15: 16-bit reload timer (with event count function) MB90580 series 15.3.1 timer control status register (tmcsr) figure 15.3.1a timer control status register controls the operation mode and interrupts for the 16-bit timer. only modify bits other than uf, cnte, and trg when cnte = 0. [bits 11, 10] csl1, csl0 (clock select 1, 0) the count clock select bits. the following tmable lists the selected clock sources.ll csl1 csl0 clock source (machine cycle f = 16 mhz) 00 f /2 1 (0.125 m s) 01 f /2 3 (0.5 m s) 10 f /2 5 (2.0 m s) 11 external event count mode 15 14 13 12 11 10 9 8 csl1 csl0 mod2 mod1 y t (r/w)(r/w)(r/w)(r/w) (0) (0) (0) (0) bit number read/write initial value timer control status register (upper) 7 6 5 4 3 2 1 0 mod0 oute outl reld inte uf cnte trg (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (0) (0) (0) tmcsr0-2 y t bit number timer control status register (lower) read/write initial value address: ch0 000048 h ch1 00004c h ch2 000050 h address: ch0 000049 h ch1 00004d h ch2 000051 h tmcsr0-2 (low) (high) 15.3 registers and register details MB90580 series chapter 15: 16-bit reload timer (with event count function) 211 [bits 9, 8, 7] mod2, mod1, mod0 these bits set the operation mode and i/o pin functions. the mod2 bit selects the i/o functions. when mod2 = 0, the input pin functions as a trigger input. in this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds. when mod2 = 1, the timer operates in gate counter mode and the input pin functions as a gate input. in this mode, the counter only counts while an active level is input to the input pin. the mod1 and 0 bits set the pin functions for each mode. the following tables list the mod2, 1, 0 bit settings [bit 6] oute output enable bit. the tout pin functions as a general-purpose port when this bit is 0 and as the timer output pin when this bit is 1. in reload mode, the output waveform toggles. in one-shot mode, tout outputs a square waveform that indicates that counting is in progress. note: for reload timer 1 and 2, tout is multiplexed with p94/out0 and p95/out1 respectively. if output capture is enabled, it has higher priority than reload timer output. [bit 5] outl this bit sets the output level for the tout pin. when outl is 0 or 1, the output pin level is oppo- site internal clock mode (csl0, 1 = 00, 01, or 10) mod2 mod1 mod0 input pin function active edge or level 00 0 trigger disabled 00 1 trigger input rising edge 01 0 y falling edge 01 1 y both edges 1 0 gate input l level 1 1 y h level event counter mode (csl0,1 = 11) mod2 mod1 mod0 input pin function active edge or level x 00 01 trigger input rising edge 10 y falling edge 11 y both edges note: bits marked as x in the table can be set to any value. 15.3 registers and register details 212 chapter 15: 16-bit reload timer (with event count function) MB90580 series [bit 4] reld (reload) this bit enables reload operations. when reld is 1, the timer operates in reload mode. in this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000 h to ffff h ). when reld is 0, the timer operates in one-shot mode. in this mode, the count operation stops when an underflow occurs due to the counter value changing from 0000 h to ffff h .. [bit 3] inte (interrupt enable) timer interrupt request enable bit. when inte is 1, an interrupt request is generated when the uf bit changes to 1. when inte is 0, no interrupt request is generated, even when the uf bit changes to 1. [bit 2] uf (underflow) timer interrupt request flag. uf is set to 1 when an underflow occurs (when the counter value changes from 0000 h to ffff h ). cleared by writing 0 or by the intelligent i/o service. writing 1 to this bit has no meaning. read as 1 by read-modify-write instructions. [bit 1] cnte (count enable) timer count enable bit. writing 1 to cnte sets the timer to wait for a trigger. writing 0 stops count operation. [bit 0] trg (trigger) software trigger bit. writing 1 to trg applies a software trigger, causing the timer to load the reload register contents to the counter and start counting. writing 0 has no meaning. reading always returns 0. applying a trigger using this register is only valid when cnte = 1. writing 1 has no effect if cnte = 0. oute reld outl output waveform 0 x x general-purpose port 100 output an h level square waveform during counting. 101 output an l level square waveform during counting. 110 toggle output. l level at count start. 111 toggle output. h level at count start. 15.3 registers and register details MB90580 series chapter 15: 16-bit reload timer (with event count function) 213 15.3.2 tmr (16-bit timer register)/tmrlr (16-bit reload register) figure 15.3.2a 16-bit timer register and 16-bit reload register n tmr contents (for reading) reading this register reads the count value of the 16-bit timer. the initial value is undefined. always read this register using word move instructions. n tmrlr contents (for writing) the 16-bit reload register holds the initial count value. the initial value is undefined. always write to this register using word transfer instructions. 15 14 13 12 11 10 9 8 ch1 00003f h y t (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) address: ch0 00003b h read/write initial value 16-bit timer register (upper)/ 16-bit reload register (upper) 7 6 5 4 3 2 1 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (x) (x) (x) (x) (x) (x) (x) (x) tmr0-2/ ch1 00003e h y t tmrlr0-2 bit number bit number 16-bit timer register (lower)/ address: ch0 00003a h 16-bit reload register (lower) read/write initial value address: ch0 00004b h ch1 00004f h ch2 000053 address: ch0 00004a h ch1 00004e h ch2 000052 h tmr0-2/ tmrlr0-2 (high) (low) 15.4 operation 214 chapter 15: 16-bit reload timer (with event count function) MB90580 series 15.4 operation 15.4.1 internal clock operation the machine clock divided by 2 1 , 2 3 , or 2 5 can be selected as the clock sources for operating the timer from an internal divide clock. the external input pin can be selected as either a trigger input or gate input by a register setting. writing 1 to both the cnte and trg bits in the control register enables and starts counting simul- taneously. using the trg bit as a trigger input is always available when the timer is enabled (cnte = 1), regardless of the operation mode. figure 15.4.1a shows counter activation and counter operation. a time period t (t: machine cycle) is required from the counter start trigger being input until the reload register data is loaded into counter. figure 15.4.1a counter activation and operation t -1 -1 -1 count clock counter data load cnte (bit) trg (bit) reload data 15.4 operation MB90580 series chapter 15: 16-bit reload timer (with event count function) 215 15.4.2 underflow operation an underflow is defined for this timer as the time when the counter value changes from 0000 h to ffff h . therefore, an underflow occurs after (reload register setting + 1) counts. if the reld bit in the control register is 1 when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues. when reld is 0, counting stops with the counter at ffff h . the uf bit in the control register is set when the underflow occurs. if the inte bit is 1 at this time, an interrupt request is generated. figure 15.4.2a shows the operation when an underflow occurs. figure 15.4.2a underflow operation 0000 h -1 -1 -1 [reld=1] count clock counter data load underflow set 0000 h ffff h [reld=0] count clock counter reload data underflow set 15.4 operation 216 chapter 15: 16-bit reload timer (with event count function) MB90580 series 15.4.3 input pin functions (for internal clock mode) the tin pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. when used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler. input a pulse width of at least 2t (t is the machine cycle) to tin. figure 15.4.3a shows the operation of trigger input. figure 15.4.3a trigger input operation when used as a gate input, the counter only counts while the active level specified by the mod0 bit of the control register is input to the tin pin. in this case, the count clock continues to operate unless stopped. the software trigger can be used in gate mode, regardless of the gate level. input a pulse width of at least 2t (t is the machine cycle) to the tin pin. figure 15.4.3b shows the operation of gate input. figure 15.4.3b gate input operation 15.4.4 external event counter the tin pin functions as an external event input pin when an external clock is selected. the counter counts on the active edge specified in the register. input a pulse width of at least 4t (t is the machine cycle) to the tin pin. -1 -1 -1 -1 2t- 2.5t tin count clock prescaler clear rising edge detected reload data counter load -1 -1 -1 tin count clock counter when mod0 = 1 (count when h is input) 15.4 operation MB90580 series chapter 15: 16-bit reload timer (with event count function) 217 15.4.5 output pin functions in reload mode, the tout pin performs toggle output (inverts at each underflow). in one-shot mode, the tout pin functions as a pulse output that outputs a particular level while the count is in progress. the outl bit of the control register sets the output polarity. when outl = 0, the initial value for toggle output is 0 and the one-shot pulse output is 1 while the count is in progress. the output waveforms are oppo- site when outl = 1. figure 15.4.5a output pin functions (1) figure 15.4.5b output pin functions (2) 15.4.6 intelligent i/o service (i 2 os) function and interrupts the timer includes a circuit that supports i 2 os. the timer can activate i 2 os when an underflow occurs. i 2 os can be used with both timers on this product. however, as both timers (ch0 and ch1) are connected to the same interrupt control register (icrx) in the interrupt controller, ch0 and ch1 cannot be assigned to different i 2 os services. also, as the two timers have different interrupt vectors, they can be assigned to two different interrupt services. however, as ch0 and ch1 share an interrupt control register as described above, the same interrupt level applies to both channels. tout cnte [reld=1, outl=0] count start underflow trigger general-purpose port level is opposite when outl = 1. tout cnte waiting for a trigger [reld=0, outl=0] underflow trigger level is opposite when outl = 1. general-purpose port 15.4.7 counter operation state the counter state is determined by the cnte bit in the control register and the internal wait signal. avail- able states are: cnte = 0 and wait = 1 (stop state), cnte = 1 and wait = 1 (wait state for trig- ger), and cnte = 1 and wait = 0 (run state). figure 15.4.7a shows the transitions between each state. figure 15.4.7a counter state transitions stop wait run cnte=0, wait=1 cnte=1, wait=1 cnte=1, wait=0 cnte=0 cnte=1 trg=0 cnte=0 cnte=1 trg=1 trg=1 trg=1 relduf reset counter: stores the value when counting stopped. undefined immediately after a reset. counter: stores the value when counting stopped. undefined just after a reset until loaded. counter: running load contents of the reload register to the counter. load cnte=1, wait= 0 state transitions by hardware state transitions by register access load complete reld uf chapter 16: a/d converter 16.1 outline the a/d converter converts analog input voltages into digital values. the a/d converter has the following features: ? conversion time: 5.2 m s min. per channel (at 16 mhz machine clock) ? rc sequential compare conversion format with sample and hold circuit ? 10-bit resolution ? analog input selected from eight channels by programming single conversion mode: one channel is selected for conversion. scan conversion mode: voltages in multiple consecutive channels are converted. up to eight channels can be programmed. continuous conversion mode: voltages in the specified channel are converted repeatedly. stop conversion mode: voltages in a single channel are converted, then the system pauses and stands by for the next activation. (the conversion start points can be synchronized.) ? at the end of a/d conversion, a relevant interrupt request can be issued to the cpu. this interrupt can be used to activate i2os, which transfers a/d conversion result data to memory. this feature is suitable for continuous processing. ? the activation factors can be selected from software, external trigger (falling edge), or timer (rising edge). 16.2 block diagram 220 chapter 16: a/d converter MB90580 series 16.2 block diagram figure 16.2a block diagram of a/d converter adtg adcs1, 2 adcr1, 2 avcc avr avss mpx an0 an1 an2 an3 an4 an5 an6 an7 input circuit sample and hold circuit comparator d/a converter sequential compare register decoder data register f 2 mc-16lx bus a/d control register 1 a/d control register 2 activation by trigger activation by timer ppg01 output operation clock prescaler 16.3 registers and register details MB90580 series chapter 16: a/d converter 221 16.3 registers and register details figure 16.3a registers of a/d converter address : 000039 h 15 14 13 12 11 10 9 8 ans0 ane2 ane1 ane0 ans1 76543 2 10 ans2 md1 md0 address : 000036 h st1 st0 ct1 ct0 sts1 sts0 strt da paus 15 14 13 12 11 10 9 8 inte busy int address : 000037 h adcs2 (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (w) (r/w) read/write control status registers (upper byte) bit number adcs1 (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number adcr2 data registers (upper byte) 76543 2 10 address : 000038 h d7 d6 d5 d4 d3 d2 d1 d0 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r) (r) (r) (r) (r) (r) (r) (r) read/write bit number adcr1 control status registers (lower byte) (0) (0) (0) (0) (1) ( ) (x) (x) initial value (w) (w) (w) (w) (w) ( ) (r) (r) read/write reserved d8 d9 data registers (lower byte) 16.3 registers and register details 222 chapter 16: a/d converter MB90580 series 16.3.1 control status registers (adcs1 and adcs2) these registers are used to control the a/d converter and display the status. figure 16.3.1a control status registers note: do not update adcs1 during a/d conversion. [bit 15] busy (busy flag and stop): read: this bit indicates the a/d converter operation. this bit is set when the a/d conversion is activated, and cleared when the conversion ends. write: writing '0' to this bit during a/d conversion forces the conversion to terminate. this features is used for forced stop in continuous or stop mode. '1' cannot be written to the operation display bit. with a read-modify-write instruction. '1' is read from this bit. in single mode, this bit is cleared at the end of a/d conversion. in continuous or stop mode, this bit is not cleared until conversion is stopped by writing '0.' this bit is initialized to '0' upon a reset. do not perform forced termination and activation by software simultaneously. (busy=0, strt=1) [bit 14] int (interrupt): a data display bit this bit is set when conversion data is written to adcr. an interrupt request is issued if this bit is set while bit 5 (inte) is '1.' in addition, i2os is activated if it is enabled. writing '1' has no effect. this bit is cleared by writing '0' or by an i2os interrupt clear signal. note: to clear this bit by writing '0,' ensure that a/d conversion is not in progress. this bit initialized to '0' upon a reset. [bit 13] inte (interrupt enable): this bit is used to enable or disable interrupts at the end of conversion.. set this bit when using i2os. i2os is activated when an interrupt request is issued. upon a reset, this bit is initialized to '0.' 0 interrupts are disabled. [initial value] 1 interrupts are enabled. ans0 ane2 ane1 ane0 ans1 76543 2 10 ans2 md1 md0 address : 000036 h sts1 sts0 strt da paus 15 14 13 12 11 10 9 8 inte busy int address : 000037 h adcs2 (0) (0) (0) (0) (0) (0) (0) (0) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (w) (r/w) read/write control status registers (upper byte) bit number adcs1 (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write control status registers (lower byte) 16.3 registers and register details MB90580 series chapter 16: a/d converter 223 [bit 12] paus (a/d conversion pause): this bit is set when the a/d conversion is paused. only one register is available for storing the a/d conversion result. therefore, unless the conversion results are transferred by i2os, the result data would be continuously updated and destroyed in contin- uous conversion. to prevent the above condition, the system is designed so that a data register value must be trans- ferred by i2os before the next conversion data is saved. a/d conversion pauses during that period. a/d conversion is resumed at the end of transfer by i2os. this register is valid only when i2os is used. * for the conversion data protection function, see section 2.7.4, "operations." upon a reset, this bit is initialized to '0.' [bits 11 and 10] sts1 and sts0 (start source select): upon a reset, these bits are initialized to '00.' these bits are used to select the a/d conversion activation factor. in a mode allowing two or more activation factors, a/d conversion is activated by the factor that is input first. the activation factor changes as soon as it is updated. thus, take care when updating it during a/d conversion. * the external pin trigger is detected by the falling edge. if this bit is updated to external trigger activation while the external trigger input level is 'l,' a/d may be activated at once. * when timer is selected, ppg1 output is selected. [bit 9] strt (start): a/d conversion is activated when '1' is written to this bit. to reactivate a/d conversion, write '1' to this bit again. in stop mode, restart is disabled due to the operation functions. upon a reset, this bit is initialized to '0.' note: do not perform forced termination and activation by software simultaneously. (busy=0, strt=1) [bit 8] da this is a test bit. always write '0' to this bit. sts1 sts0 function 0 0 activation by software 0 1 activation by external pin trigger and software 1 0 activation by timer and software 1 1 activation by external pin trigger, timer, and software 16.3 registers and register details 224 chapter 16: a/d converter MB90580 series [bits 7 and 6] md1 and md0 (a/d converter mode set): these bits are used to set the a/d converter operation mode. single mode: a/d conversion is continuously performed from the channel specified with ans2 to ans0 to the channel specified with ane2 to ane0. the conversion stops once it has been done for all these channels. continuous mode: a/d conversion is repeatedly performed from the channel specified with ans2 to ans0 to the channel specified with ane2 to ane0. stop mode: a/d conversion is performed from the channel specified with ans2 to ans0 to the channel specified with ane2 to ane0, pausing for each channel. the a/d conversion is resumed upon an activation factor. upon a reset, these bits are initialized to '00.' note: when activated in continuous or stop mode, a/d conversion continues until it is stopped by the busy bit. note: the conversion is stopped by writing '0' to the busy bit. note: in single, continuous, or stop mode, reactivation is disabled regardless of the activa- tion factor (timer, external trigger, or software). [bits 5, 4, and 3] ans2, ans1, and ans0 (analog start channel set): use these bits to specify the start channel for a/d conversion. when the a/d converter is activated, a/d conversion starts from the channel selected with these bits. * read during a/d conversion, the current conversion channel is read from these bits. if the system is stopped in stop mode, the previous conversion channel is read. * upon a reset, these bits are initialized to '000.' md1 md0 operation mode 0 0 single mode. reactivation during operation is allowed. 0 1 single mode. reactivation during operation is not allowed. 10 continuous mode. reactivation during operation is not allowed. 1 1 stop mode. reactivation during operation is not allowed. ans2 ans1 ans0 start channel 000 an0 001 an1 010 an2 011 an3 100 an4 101 an5 110 an6 111 an7 16.3 registers and register details MB90580 series chapter 16: a/d converter 225 [bits 2, 1, and 0] ane2, ane1, and ane0 (analog end channel set): use these bits to set the a/d conversion end channel. * when the same channel is written to ane2 to ane0 and ans2 to ans0, conversion is performed for one channel only (single conversion). * in continuous or stop mode, operation returns to the start channel specified in ans2 to ans0 after the conversion is completed for the channel specified in ane2 to ane0. * if the ans value is smaller than the ane value, conversion starts from the ans channel. then, once conversion is complete up to channel 7, operation returns to channel 0 and conversion is performed up to the ane channel. * upon a reset, these bits are initialized to '000.' example: ans=6, ane=3, single mode conversion is performed in the following sequence: ch6, ch7, ch0, ch1, ch2, ch3 ane2 ane1 ane0 end channel 000 an0 001 an1 010 an2 011 an3 100 an4 101 an5 110 an6 111 an7 16.3 registers and register details 226 chapter 16: a/d converter MB90580 series 16.3.2 adcr1 and adcr0 (data registers) figure 16.3.2a data registers [bit 15] this is reserved bit. this bit should be written to 1 before ad conversion. never write 0 to this bit. note: reading this bit always returns 1. [bit 14, 13] : st1, st0 (sampling time) these bits is used for setting the sampling time in terms of machine cycle. note: reading these bits always return 1. st1 st0 sampling time machine cycle sampling time 0 0 64 machine cycle 4ms at 16mhz machine clock 01 reserved 10 reserved 1 1 4096 machine cycle 256ms at 16mhz machine clock address : 000039 h 15 14 13 12 11 10 9 8 st1 st0 ct1 ct0 bit number adcr2 data registers (upper byte) 76543 2 10 address : 000038 h d7 d6 d5 d4 d3 d2 d1 d0 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r) (r) (r) (r) (r) (r) (r) (r) read/write bit number adcr1 (0) (0) (0) (0) (1) ( ) (x) (x) initial value (w) (w) (w) (w) (w) ( ) (r) (r) read/write reserved d8 d9 data registers (lower byte) 16.3 registers and register details MB90580 series chapter 16: a/d converter 227 [bit 12, 11] : ct1, ct0 (compare time) these bits is used for setting the comparsion time in terms of machine cycle. note1: when the bits is set to 00, the machine clock should not be higher than 8mhz. note2: reading these bits always return 1. [bit 9 to bit 0] : d9 to d0 (adcr1:1,0 and adcr0) adcr1:1,0 and adcr0 stores the ad conversion result. these register values are updated each time conversion is completed. usually, the final conversion value is stored in these bits. upon a reset, these registers are undefined. the conversion data protection function is available. see section 2.7.4, "operations." note: ensure that no data is written to these registers during a/d conversion. ct1 ct0 comparsion time machine cycle comparsion time 0 0 176 machine cycle 22ms at 8mhz machine clock 0 1 352 machine cycle 22ms at 16mhz machine clock 10 reserved 11 reserved 16.4 operations 228 chapter 16: a/d converter MB90580 series 16.4 operations the a/d converter operates in the sequential compare format, and has a 8-bit resolution. since the a/d converter has only one register (8 bits) for storing the conversion result, the conversion data registers (adcr0) are updated each time conversion is completed. thus, the a/d converter must not be used alone for continuous conversion. use the f 2 mc-16 intelligent i/o service function to transfer con- verted data to memory while conversion is in progress. the operation modes are explained below. (1) single mode in this mode, the converter sequentially converts the analog inputs specified with the ans and ane bits. the converter stops operation after the conversion is completed for the end channel specified with the ane bits. if the start and end channels are the same (ans=ane), conversion is performed only for one channel. example: ans = 0 0 0 , ane = 0 1 1 start ? an0 ? an1 ? an2 ? an3 ? end ans = 0 1 0 , ane = 0 1 0 start ? an2 ? end (2) continuous mode in this mode, the converter sequentially converts the analog inputs specified with the ans and ane bits. after the conversion is completed for the end channel specified with the ane bits, conversion is repeated from the analog inputs of the ans. if the start and end channels are the same (ans=ane), conversion for one channel is repeated. example: ans = 0 0 0 , ane = 0 1 1 start ? an0 ? an1 ? an2 ? an3 ? an0 repeat ans = 0 1 0 , ane = 0 1 0 start ? an2 ? an2 ? an2 repeat in continuous mode, conversion is repeated until '0' is written to the busy bit. (writing '0' to the busy bit forces the operation to end.) if the operation is terminated forcibly, conversion stops before conver- sion is completed. (upon a forced termination, the conversion register stores the previous data that has been converted completely.) ? ...... ? ...... 16.4 operations MB90580 series chapter 16: a/d converter 229 (3) stop mode in this mode, the converter sequentially converts the analog inputs specified with the ans and ane bits, pausing each time conversion for one channel is completed. to release pausing, activate the a/d converter again. after the conversion is completed for the end channel specified with the ane bits, conversion is repeated from the analog inputs of the ans. if the start and end channels are the same (ans=ane), conversion is performed only for one channel. example: ans = 0 0 0 , ane = 0 1 1 start ? an0 ? end ? restart ? an1 ? end ? restart ? ? an2 ? end ? restart ? ? an3 ? end ? restart ? an0 repeat ans = 0 1 0 , ane = 0 1 0 start ? an2 ? end ? restart ? an2 ? end ? restart? ? an2 repeat only the activation factors specifies with sts1 and sts0 are used. in this mode, start of conversion can be synchronized. (4) conversion using i 2 os sample flow from a/d conversion activation to transfer of converted data (continuous mode) figure 16.4a flow chart of a/d conversion ? ...... ? ...... starting a/d conversion sample and hold conversion end of conversion issuing interrupt starting i 2 os transferring data clearing interrupt interrupt processing the portion indicated by the star ( ) is determined according to the i 2 os settin 16.4 operations 230 chapter 16: a/d converter MB90580 series usage l starting i 2 os in single mode ?to terminate conversion after analog inputs an1 to an3 are converted ?to transfer conversion data sequentially to addresses 200h to 206h ?to start conversion by software ?to use the highest interrupt level i 2 os setting mov icr3 #08h .............................................. ? mov bapl, #00h .............................................. - mov bapm, #02h .............................................. ? mov baph, #00h .............................................. mov iscs, #18h .............................................. mov ioa, #38h .............................................. mov dct, #03h .............................................. 2 a/d converter setting mov adcs1 #0bh .......................................................... 3 mov adcs2 #a2h .......................................................... interrupt sequence reti .......................................................... ? specifies the highest interrupt level, i2os activation upon an interrupt, and the descriptor address. -? specifies the transfer destination address of converted data. specifies word data transfer. the transfer destination address is incremented after transfer. data is transferred from i/o to memory. transfer is terminated in response to a request from a resource. 2 i 2 os transfer is performed three times. this count is the same as the conversion count. 3 specifies single mode, start channel an1, and end channel an3. specifies activation by software and start of a/d conversion. specifies return from an interrupt. icr3 : interrupt control register bapl : buffer address pointer, low-order bapm : buffer address pointer, medium-order baph : buffer address pointer, high-order iscs : i 2 os status register i/oa : i/o address counter dct : data counter activation an1 ? interrupt ? i 2 os transfer an2 ? interrupt ? i 2 os transfer an3 ? interrupt ? i 2 os transfer end interrupt sequenc parallel processing 16.4 operations MB90580 series chapter 16: a/d converter 231 usage l starting i 2 os in continuous mode ?to convert analog inputs an3 to an5 and obtain two conversion data items for each channel ?to transfer conversion data sequentially to addresses 600h to 60ch ?to start conversion by external edge input to use the highest interrupt level i 2 os setting mov icr3 #08h ............................................... ? mov bapl, #00h ............................................... - mov bapm, #06h ............................................... ? mov baph, #00h ............................................... mov iscs, #08h ............................................... mov i / oa, #38h ............................................... mov dct, #06h ............................................... 2 a/d converter setting mov adcs1 #9dh .......................................................... 3 mov adcs2 #a4h .......................................................... interrupt sequence mov adcs2 #00h .......................................................... ret ? specifies the highest interrupt level, i2os activation upon an interrupt, and the descriptor address. -? specifies the transfer destination address of converted data. specifies word data transfer. the transfer destination address is incremented after transfer. data is transferred from i/o to memory. transfer is terminated in response to a request from a resource. transfer source address 2 i 2 os transfer is performed six times. data is transferred for three channels 2. 3 specifies continuous mode, start channel an3, and end channel an5. specifies activation by external edge and start of a/d conversion. specifies return from an interrupt. icr3 : interrupt control register bapl : buffer address pointer, low-order bapm : buffer address pointer, medium-order baph : buffer address pointer, high-order iscs : i 2 os status register i/oa : i/o address counter dct : data counter a ctivation an3 ? interrupt ? i 2 os transfer an4 ? interrupt ? i 2 os transfer an5 ? interrupt ? i 2 os transfer interrupt sequenc end after six transfers 16.4 operations 232 chapter 16: a/d converter MB90580 series usage l starting i 2 os in stop mode ?to convert analog input an3 12 times at fixed intervals ?to transfer conversion data sequentially to addresses 600h to 618h ?to start conversion by external edge input to use the highest interrupt level i 2 os setting mov icr3 #08h .............................................. ? mov bapl, #00h .............................................. - mov bapm, #06h .............................................. ? mov baph, #00h .............................................. mov iscs, #08h .............................................. mov i / oa, #38h .............................................. mov dct, #0ch .............................................. 2 a/d converter setting mov adcs1 #dbh .......................................................... 3 mov adcs2 #a4h .......................................................... interrupt sequence mov adcs2 #00h .......................................................... ret ? specifies the highest interrupt level, i2os activation upon an interrupt, and the descriptor address. -? specifies the transfer destination address of converted data. specifies word data transfer. the transfer destination address is incremented after transfer. data is transferred from i/o to memory. transfer is terminated in response to a request from a resource. transfer source address 2 i 2 os transfer is performed 12 times. 3 specifies continuous mode, start channel an3, and end channel an3 (one-channel conversion). specifies activation by external edge and start of a/d conversion. specifies return from an interrupt. icr3 : interrupt control register bapl : buffer address pointer, low-order bapm : buffer address pointer, medium-order baph : buffer address pointer, high-order iscs : i 2 os status register i/oa :i/o address counter dct : data counter activation an3 ? interrupt ? i 2 os transfer stop activation by external edge interrupt sequenc after 12 transfers end 16.4 operations MB90580 series chapter 16: a/d converter 233 (5) conversion data protection the a/d converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using i 2 os. since there is only one conversion data register, its value is updated each time conversion is com- pleted. thus, continuous data conversion results in the loss of the previous data due to storage of the new data. to prevent this situation, the a/d converter pauses after conversion if the previous data item has not been transferred to memory by i 2 os. the converted data is not saved until the previous data is transferred to memory. the pause is released after data is transferred to memory by i 2 os. if the previous data has been transferred to memory, the a/d converter continues operation without pausing. note: * this function is related to the int and inte bits of adcs2. the data protection function operates only when interrupts are enabled (inte=1). if interrupts are disabled (inte=0), this function is disabled. continuous a/d conversion results in loss of previous data, since the converted data items are saved to the register one after another. if i 2 os is not used while interrupts are enabled (inte=1), the int bit is not cleared. thus, the data pro- tection function works and the a/d converter pauses. in this case, clearing the int bit in the interrupt sequence releases the pause. if the a/d converter is pausing during i 2 os operation, disabling interrupts may restart the a/d converter. in this case, the value in the conversion data register may be changed without being transferred. restarting the a/d converter while it is pausing destroys the standby data. flow of data protection function (when i 2 os is used) figure 16.4b flow chart of data protection function no yes yes no setting i 2 os starting continuous a/d conversion ending first conversion saving the result in the data register ending second conversion end i 2 os? saving the result in the data register ending third conversion continued ending the last conversion end the flow while a/d converter is stopped is omitted. *1: restarting the converter while paused destroys starting i 2 os pausing a/d conversion *1 interrupt routine stooping a/d conversion starting i 2 os starting i 2 os end i 2 os? the standby conversion data. 16.5 notes on use 234 chapter 16: a/d converter MB90580 series 16.5 notes on use to start the a/d converter upon an external trigger or internal timer, a/d activation factor bits sts1 and sts0 of the adcs2 register are used. ensure that the input values of the external trigger or internal timer are inactive. if the values are active, a/d conversion may start immediately. when setting sts1 and sts0, ensure that '1' (input) is specified for adtg and '0' (output) is specified for the internal timer (timer 2). 16.5.1 other considerations always write '1' to the ader bit corresponding to a pin used as analog input. port 5 pins are controlled as described below. 0: port input mode 1: analog input mode '1' is set upon a reset. ade3 ade2 ade1 ade0 ade4 15 14 13 12 11 10 9 8 ade5 ade7 ade6 address: 00001c h bit r/w r/w r/w r/w r/w r/w r/w r/w (1) (1) (1) (1) (1) (1) (1) (1) initial value read/write ader analog input enable register chapter 17: d/a converter 17.1 outline this is an r-2r format d/a converter, having an eight-bit resolution. the d/a converter has two channels. output control can be performed independently for the two channels using the d/a control register. 17.2 block diagram 236 chapter 17: d/a converter MB90580 series 17.2 block diagram figure 17.2a block diagram of d/a cobverter f 2 mc-16lx bus da 17 da 16 da 15 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 04 da 03 da 02 da 01 da 00 da17 da16 da15 da11 dvr 2r r 2r r da10 2r r 2r 2r dae1 dae0 da07 da06 da05 da01 dvr 2r r 2r r da00 2r r 2r 2r standby control da output ch1 da output ch0 standby control 17.3 registers and register details MB90580 series chapter 17: d/a converter 237 17.3 registers and register details figure 17.3a register of d/a converter da07 da06 da05 da04 da03 da02 da01 da00 da17 da16 da15 da14 da13 da12 da11 da10 d/a converter data register 1 address : 00003d h 15 14 13 12 11 10 9 8 76543 2 10 address : 00003a h 15 14 13 12 11 10 9 8 address : 00003b h dat1 (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number dat0 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number dacr1 76543 2 10 address : 00003c h (-) (-) (-) (-) (-) (-) (-) (0) initial value (-) (-) (-) (-) (-) (-) (-) (r/w) read/write initial value read/write bit number dacr0 dae1 dae0 d/a converter data register 0 d/a control register 1 d/a control register 0 (-) (-) (-) (-) (-) (-) (-) (0) (-) (-) (-) (-) (-) (-) (-) (r/w) 17.3 registers and register details 238 chapter 17: d/a converter MB90580 series 17.3.1 dat0/1 ( d/a data register) [bits 15 to 8] da17 to da10 these bits are used to set the output voltage of d/a converter ch1. these bits are not initialized upon a reset. these bits are readable and writable. [bits 7 to 0] da07 to da00 these bits are used to set the output voltage of d/a converter ch0. these bits are not initialized upon a reset. these bits are readable and writable. 17.3.2 dacr0/1 ( d/a control register) [bit 0] dae1 and dae0 these bits are used to enable or disable the d/a converter output. dae1 controls channel 1 output, while dae0 controls channel 0 output. when '1' is written to these bits, d/a output is enabled. when '0' is set, d/a output is disabled. these bits are initialized to '0' upon a reset. these bits are readable and writable. da07 da06 da05 da04 da03 da02 da01 da00 da17 da16 da15 da14 da13 da12 da11 da10 d/a converter data register 1 76543 2 10 address : 00003a h 15 14 13 12 11 10 9 8 address : 00003b h dat1 (x) (x) (x) (x) (x) (x) (x) (x) initial value bit number (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number dat0 (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write d/a converter data register 0 address : 00003d h 15 14 13 12 11 10 9 8 bit number dacr1 76543 2 10 address : 00003c h (-) (-) (-) (-) (-) (-) (-) (0) initial value (-) (-) (-) (-) (-) (-) (-) (r/w) read/write initial value read/write bit number dacr0 dae1 dae0 d/a control register 1 d/a control register 0 (-) (-) (-) (-) (-) (-) (-) (0) (-) (-) (-) (-) (-) (-) (-) (r/w) 17.4 operations MB90580 series chapter 17: d/a converter 239 17.4 operations d/a output is started by writing a desired d/a output value to the d/a data register (dadr) and setting '1' to the enable bit for the corresponding d/a output channel in the d/a control register (dacr). disabling d/a output turns off the analog switch that is inserted serially into the output of each d/a con- verter channel. in addition, the d/a converter is internally cleared to '0' and the path of the dc current is shut down. this also applies in stop mode. table 17.4a shows the theoretical values of d/a converter output voltages the d/a converter output voltages are between 0 v and 255/256 v dvr. the output voltage range is changed by regulating the dvr voltage externally. the d/a converter output does not have an internal buffer amplifier. since an analog switch (=100 w ) is serially inserted into the output, allow sufficient settling time when applying an external output load. table 17.4a theoretical values of d/a converter output voltages values written to da07 to da00 and da17 to da10 theoretical values of output voltages 00 h 0/256 dvr (=0 v) 01 h 1/256 dvr 02 h 2/256 dvr fd h 253/256 dvr fe h 254/256 dvr ff h 255/256 dvr chapter 18: pulse width counter (pwc) timer 18.1 outline this module is a multi-function 16-bit up-counter with a reload function and a function for counting pulse widths on the input signal. the module hardware consists of a 16-bit up-counter, input pulse divider, divide ratio control register, four count input pins, one pulse output pin, and a 16-bit control register. these per- form the following functions. timer function: ? interrupt requests can be generated at specified time intervals. ? a pulse signal can be output synchronized with the timer period. ? the counter clock can be selected from three internal clocks. pulse width count function: ? measures the time between events on an external pulse input. ? the counter clock can be selected from three internal clocks. ? count modes h pulse width ( y to ? )/l pulse width ( ? to y ) rising edge period ( y to y )/falling edge period ( ? to ? ) inter-edge count ( y or ? to ? or y ) ? using the 8-bit input divider, the module can divide an input pulse signal by 2 2n (n = 1, 2, 3, 4) and measure the period. ? an interrupt request can be generated on count completion. ? single-shot or continuous counting can be selected. the MB90580 series contains one pwc timer channels. 18.2 block diagram 242 chapter 18: pulse width counter (pwc) timer MB90580 series 18.2 block diagram figure 18.2a lock diagram of pulse width counter timer ffmc-16 bus write enable pwcr read error detection reload data transfer overflow flag set control bit output start edge count start edge count end edge count end overflow interrupt end edge divider timer clear clock count enable divide ratio overflow divider clear internal clock pwcr edge detect pwcsr 16-bit up-count timer err 16 16 16 16 control circuit selection interrupt request on/off request selection err pis1 pis0 cks1 cks0 divr 15 2 8-bit divider clock divider 2 2 2 3 cks1 cks0 (machine clock/4) selection f.f pot pwc 18.3 regiaters and register details MB90580 series chapter 18: pulse width counter (pwc) timer 243 18.3 regiaters and register details figure 18.3a register of pulse width counter timer 15 14 13 12 11 10 9 8 ovir ovie err pout edie edir strt stop address : 000055 h bit number pwcsr (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r) (r/w) (r/w) (r/w) (r) (r/w) read/write address : 000058 h 76543 2 10 bit number divr initial value read/write divide ratio control register div1 div0 (-) (-) (-) (-) (-) (-) (0) (0) (-) (-) (-) (-) (-) (-) (r/w) (r/w) address : 000086 h 76543 2 10 bit number rncr initial value read/write pwc noise cancelling register sw1 sw0 en (-) (-) (-) (-) (-) (0) (0) (0) (-) (-) (-) (-) (-) (r/w) (r/w) (r/w) pwc control status register (upper byte) (high) address : 000054 h 76543 2 10 csk0 pis1 pis0 s/c csk1 bit number pwcsr initial value read/write pwc control status register (lower byte) mod2 mod1 mod0 (0) (0) (0) (0) (0) (0) (0) (0) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (low) address : 000056 h 15 14 13 12 11 10 9 8 76543 2 10 address : 000057 h bit number (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number pwcr initial value read/write pwc data buffer register (upper byte) pwc data buffer register (lower byte) (x) (x) (x) (x) (x) (x) (x) (x) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) pwcr (high) (low) 18.3 regiaters and register details 244 chapter 18: pulse width counter (pwc) timer MB90580 series 18.3.1 pwc control status register (pwcsr) the pwcsr is used to control the operation of the pwc timer and to read the pwc timer status. [bit 15] strt (start) & [bit 14] stop (stop) these bits start, restart, and stop the 16-bit up-count timer. reading the bits returns the operating state of the timer. the bit functions are as follows. function of strt and stop bits when they are written. (operation control) meaning of the strt and stop bits when they are read. (operating status indication) after a reset: initialized to 00 b . readable and writable. note that the meanings of the bits differ for reading and writing. always read as 11 b by read-modify-write instructions regardless of the actual values. although bit manipulation instructions (such as the bit clear instruction) can be used to write to the strt and stop bits to start and stop the timer, bit manipulation instructions cannot be used to read the operating status (as these always indicate that the timer is operating). strt stop operation control function 0 0 no function. has no effect on operation. 0 1 starts or restarts the timer (count enable). note: the clear bit instruction can be used. 1 0 forcibly halts the operation of the timer (count disable). note: the clear bit instruction can be used. 1 1 no function. has no effect on operation. strt stop operating status indication 0 0 timer is halted (not started or count ended). (initial value) 1 1 timer is counting (count in progress). 15 14 13 12 11 10 9 8 ovir ovie err pout edie edir strt stop address : 000055 h bit number pwcsr (0) (0) (0) (0) (0) (0) (0) (0) initial value (r/w) (r/w) (r) (r/w) (r/w) (r/w) (r) (r/w) read/write pwc control status register (upper byte) (high) address : 000054 h 76543 2 10 csk0 pis1 pis0 s/c csk1 bit number pwcsr initial value read/write pwc control status register (lower byte) mod2 mod1 mod0 (0) (0) (0) (0) (0) (0) (0) (0) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (low) 18.3 regiaters and register details MB90580 series chapter 18: pulse width counter (pwc) timer 245 [bit 13] edir (end interrupt request) this flag indicates when counting ends in pulse width count mode. a count end interrupt request is generated if the interrupt is enabled (bit 12: edie = "1") when this bit is set. note: this bit has no meaning in timer mode. after a reset: initialized to "0". read-only. writing to the bit does not change the value. [bit 12] edie (end interrupt enable) controls the count end interrupt request in pulse width count mode as follows. note: always set to "0" during timer mode. after a reset: initialized to "0". readable and writable. [bit 11] ovir (overflow interrupt request) this flag indicates when the 16-bit up-count timer overflows from ffff h to 0000 h . operates in all modes. a timer overflow interrupt request is generated if the interrupt is enabled (bit 10: ovie = "1") when this bit is set. after a reset: initialized to "0". readable and writable. however, only writing "0" is valid. writing "1" does not change the bit value. read-modify-write instructions always read the bit as "1" regardless of the actual bit value. [bit 10] ovie (overflow interrupt enable) controls the timer overflow interrupt request as follows. after a reset: initialized to "0". readable and writable. set timing set when pulse width counting ends (when the count result is placed in pwcr). clear timing cleared by reading pwcr (the count result). 0 disable output of count end interrupt requests (do not generate an interrupt when edir is set). (initial value) 1 enable output of count end interrupt requests (generate an interrupt when edir is set). set timing set when a timer overflow occurs (ffff h to 0000 h ). clear timing cleared by writing "0" or by the extended intelligent i/o service. 0 disable output of overflow interrupt requests (do not generate an interrupt when ovir is set). (initial value) 1 enable output of overflow interrupt requests (generate an interrupt when ovir is set). 18.3 regiaters and register details 246 chapter 18: pulse width counter (pwc) timer MB90580 series [bit 9] err (error) this flag is used when continuous counting is performed in pulse width count mode. the flag indicates that the next count has completed before the previous count result has been read from pwcr. when this occurs, pwcr is overwritten with the new count result and the previous result is lost. counting continues regardless of the value of this bit. after a reset: initialized to "0". read-only. writing to the bit does not change the value. [bit 8] pout (pulse output) in timer mode, this bit is inverted each time the 16-bit up-count timer overflows from ffff h to 0000 h . the bit has no meaning in pulse width count mode. after a reset: initialized to "0". readable and writable. however, the bit can only be written to when the timer is halted (when bit 15 and bit 14: strt and stop are both "0"). the value of the bit does not change if written to during timer operation (when bit 15 and bit 14: strt and stop are both "1"). [bits 7, 6] cks1, cks0 (clock select 1, 0) these bits select the internal count clock as follows. after a reset: initialized to "00 b ". readable and writable. however, setting "11 b " is prohibited. note: changing the setting after activating the timer is prohibited. only write to these bits before starting or after halting the timer. set timing set when a count result that has not been read is overwritten by the next result. clear timing cleared by reading pwcr (the count result). set timing set when the timer overflows from ffff h to 0000 h when the value of pout is "0", or by writing "1" when the timer is halted. clear timing cleared when the timer overflows from ffff h to 0000 h when the value of pout is "1", by writing "0" when the timer is halted, or by a reset. csk1 csk0 count clock selection 00 machine cycle divided by 4 (0.25s for a 16mhz machine cycle) (initial value) 0 1 machine cycle divided by 16 (1.0s for a 16mhz machine cycle) 1 0 machine cycle divided by 32 (2.0s for a 16mhz machine cycle) 11 note: prohibited setting 18.3 regiaters and register details MB90580 series chapter 18: pulse width counter (pwc) timer 247 [bits 5, 4] pis1, pis0 (pulse input select) these bits select the input pin on which to perform pulse width counting. after a reset: initialized to "00 b ". readable and writable. note: changing the setting after activating the timer is prohibited. only write to these bits before starting or after halting the timer. note: when developing software for the MB90580 series, always set these bits to "00 b ". [bit 3] s/c (single/continuous) select the count mode as follows. after a reset: initialized to "0". readable and writable. note: changing the setting after activating the timer is prohibited. only write to these bits before starting or after halting the timer. pis1 pis0 count input pin selection 0 0 always set this value. (initial value) 0 1 setting unavailable (do not set any of these values.) 10 11 s/c count mode selection timer mode pulse width count mode 0 single-shot count mode (initial value) no reload (single-shot) halt after one count. 1 continuous count mode perform reload (reload timer) continuous counting: buffer register enabled 18.3 regiaters and register details 248 chapter 18: pulse width counter (pwc) timer MB90580 series [bits 2, 1, 0] mod2, mod1, mod0 (mod2, 1, 0) these bits select the operation mode and the pulse edges for width counting. after a reset: initialized to "000 b ". readable and writable. note: changing the setting after activating the timer is prohibited. only write to these bits before starting or after halting the timer. note: when continuous count mode is set for the settings marked with an asterisk (*), the divider circuit for the internal count clock is not cleared when the count ends so as to accumulate the number of edges. in all other modes, the divider circuit for the internal count clock is cleared when the count ends. mod2 mod1 mod0 operation mode/count edge selection 0 0 0 timer mode, no pulse output (initial value) 0 0 1 timer mode, pulse output enabled (using the pot pin): reload mode only 0 1 0 inter-edge pulse width count mode ( y or ? to ? or y )* 0 1 1 divided period count mode (using input divider) * 1 0 0 rising-edge to rising-edge count mode ( y to y ). * 1 0 1 "h" pulse width count mode( y to ? ). * 1 1 0 "l" pulse width count mode( ? to y ). * 1 1 1 falling-edge to falling-edge count mode ( ? to ? ). * 18.3 regiaters and register details MB90580 series chapter 18: pulse width counter (pwc) timer 249 18.3.2 pwc data buffer register (pwcr) (1) in timer mode in reload timer operation mode (bit 3 s/c of pwcsr = "1"), this register stores the reload value. in this case, the register is readable and writable. in single-shot timer operation mode (bit 3 s/c of pwcsr = "0"), accessing this register directly accesses the up-count timer. although both reading and writing are allowed in this mode, only write to the register when the timer is halted. the register can be read at any time to read the current timer value. (2) in pulse width count mode read-only in continuous count mode (bit 3 s/c of pwcsr = "1"), this register acts as a buffer register to store the previous count result. in this case, the register is read-only and writing does not change the register value. in single-shot count mode (bit 3 s/c of pwcsr = "0"), accessing this register directly accesses the up-count timer. the register is read-only in this mode also and writing does not change the register value. the register can be read at any time to read the current timer value. after the count ends, the register stores the count result. note: always use word transfer instructions to access this register. after a reset: initialized to "0000 h ". address : 000056 h 15 14 13 12 11 10 9 8 76543 2 10 address : 000057 h bit number (x) (x) (x) (x) (x) (x) (x) (x) initial value (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) read/write bit number pwcr initial value read/write pwc data buffer register (upper byte) pwc data buffer register (lower byte) (x) (x) (x) (x) (x) (x) (x) (x) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) pwcr (high) (low) 18.3 regiaters and register details 250 chapter 18: pulse width counter (pwc) timer MB90580 series 18.3.3 divide ratio control register (divr) this register is only used in divided period count mode (bits 2, 1, 0: mod2, 1, 0 of pwcsr = "011"). in divided period count mode, pulses input from the count pin are divided by the divide ratio set in this register and the period of the divided signal is measured. the divide ratio is selected as follows. after a reset: initialized to "00 b ". readable and writable. note: changing the setting after activating the timer is prohibited. only write to these bits before starting or after halting the timer. div1 div0 divide ratio selection 00 2 2 = divide by 4 (initial value) 01 2 4 = divide by 16 10 2 6 = divide by 64 11 2 8 = divide by 256 address : 000058 h 76543 2 10 bit number divr initial value read/write divide ratio control register div1 div0 (-) (-) (-) (-) (-) (-) (0) (0) (-) (-) (-) (-) (-) (-) (r/w) (r/w) 18.3 regiaters and register details MB90580 series chapter 18: pulse width counter (pwc) timer 251 18.3.4 pwc noise cancelling register (rncr) the pwc noise removal circuit is used for removing noises form the input signal. h level and l level detection will be applied to the input signal after it was cleaned by the noise filter. noise removal circuit is a digital low pass filter, the filter remove the high frequency components of the input signal. the noise-removed signal is called rmcsig. this signal has the same polarilty with the orginial input signal, but the there may be slight phase difference. the sw bits of the noise cancelling register specifies the noise pulse width which can be removed by the filter circuit. this noise cancelling register is a 8-bit register, when reset, all bits will be initialized to 0. [bits 2, 1] sw1, sw0 sw1 and sw0 is the clock mode selection bit which specify the noise pulse width to be removed. the timing of the following table assumes the main clock is 16mhz. [bits 0] en en bit is used for enabling this noise cancelling function. sw1 sw0 input clock noise pulse width 0 0 0.5 mhz 2.0 m s 0 1 31.25 khz 32.0 m s 1 0 15.62 khz 64.0 m s 1 1 7.81 khz 128.0 m s 0 noise cancelling function disabled (initial value) 1 noise canncelling function enabled address : 000086 h 76543 2 10 bit number rncr initial value read/write pwc noise cancelling register sw1 sw0 en (-) (-) (-) (-) (-) (0) (0) (0) (-) (-) (-) (-) (-) (r/w) (r/w) (r/w) 18.4 operations 252 chapter 18: pulse width counter (pwc) timer MB90580 series 18.4 operations (1) summary of operation this block is a multi-function timer based on a 16-bit up-count timer and incorporating a count input pin and 8-bit input divider. the block has two main functions: a timer function and a pulse width count function. two types of count clock can be selected for either function. the following describes the basic functions and operation of each of these functions. (a) timer function this function is an up-count timer which can be selected to operate in reload or single-shot mode. once started, the timer counts on each count clock. an interrupt request can be generated when an overflow from ffff h to 0000 h occurs. when an overflow occurs: ? single-shot mode: ............. the count stops. ? reload mode:.................... the timer is reloaded with the contents of the reload register and the count restarts. figure 18.4a timer operation (single-shot mode) figure 18.4b timer operation (reload mode) timer count value timer start overflow write to pwcr ovir flag set, timer stop overflow timer start ovir flag set, timer stop (the solid line is the timer count value.) (restart is disabled.) time ? ffff h 0000 h ? ? ? ? ? timer count value timer start overflow timer stop overflow timer start (the solid line is the timer count value.) time ffff h 0000 h pwcr ovir pout bit reload write to pwcr does not toggle when restarted when starting from "l" write value flag set ? reload reload reload reload reload reload t overflow overflow overflow (unless this occurs at the same time as an overflow) 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 253 (2) pulse width count function this function counts the time period between specified events on an input pulse. after the function is activated, the count does not start until the specified count start edge is input. the counter is cleared to "0000 h " and counting starts when the start edge is detected. the count halts when the end edge is detected. the count value at the end of this period is stored in the register as the pulse width. an interrupt request can be generated when the count ends or when an overflow occurs. after counting completes: ? single-shot count mode: ... operation halts. ? continuous count mode: ... the timer value is transferred to the buffer register and the count halts until the next start edge is input. figure 18.4c pulse width count operation (single-shot count mode, "h" width count mode) figure 18.4d pulse width count operation (continuous count mode, "h" width count mode) pulse being counted timer count value (the solid line is the timer count value.) timer clear count start timer start timer stop edir flag set (count end) time on the pwc0 to 3 inputs ffff h 0000 h ? ? ? ? ? pulse being counted timer count value (the solid line is the timer count value.) timer clear count start timer start timer stop edir flag set (count end) time on the pwc0 to 3 inputs ffff h 0000 h ? ? ? ? ? overflow ? data transferred to pwcr ? data transferred to pwcr timer clear timer start ovir flag set timer stop ? edir flag set 18.4 operations 254 chapter 18: pulse width counter (pwc) timer MB90580 series (3) count clock selection the timer count clock can be selected from three internal clock sources. the available clock sources are listed below. the selection is initialized to "machine cycle divided by 4" after a reset. note: always select the count clock before starting the timer. table 18.4a count clock selection pwcsr/bit7, 6:cks1, 0 selected internal count clock 00 b machine cycle divided by 4 (0.25s for a 16mhz machine cycle) (initial value) 01 b machine cycle divided by 16 (1.0s for a 16mhz machine cycle) 10 b machine cycle divided by 32 (2.0s for a 16mhz machine cycle) 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 255 (4) operation mode selection the operation mode and count mode are selected by pwcsr settings. ? operation mode setting pwcsr bits 2, 1, and 0: bits mod2, mod1, and mod0 (selects timer or pulse width count mode and specifies which edges control counting.) ? count mode setting pwcsr bit 3: s/c bit (selects single-shot or continuous counting, or reload or single-shot operation.) the following lists the operation modes selected by the mode setting bits. the initial value after a reset selects single-shot timer mode. note: always select the operation mode before starting the timer. figure 18.4e operation mode selection operation mode s/c mod2 mod1 mod0 timer single-shot timer 0 0 0 0 reload timer 1 0 0 0 setting prohibited 1 0 0 1 pulse width count y or ? to y or ? single-shot count: buffer not used 0010 counts between all edges continuous count: buffer used 1010 divided period count single-shot count: buffer not used 0011 (divide by 1 to 256) continuous count: buffer used 1011 y to y single-shot count: buffer not used 0100 rising-edge to rising- edge count continuous count: buffer used 1100 y to ? single-shot count: buffer not used 0101 "h" pulse width count continuous count: buffer used 1101 ? to y single-shot count: buffer not used 0110 "l" pulse width count continuous count: buffer used 1110 ? to ? single-shot count: buffer not used 0111 falling-edge to falling- edge count continuous count: buffer used 1111 18.4 operations 256 chapter 18: pulse width counter (pwc) timer MB90580 series (5) starting and stopping the timer and pulse width count starting, restarting, and forcibly halting each operation is performed using bits 15 and 14 (strt and stop) of pwcsr. writing "0" to the strt bit starts or restarts operation and writing "0" to the stop bit forcibly halts operation. however, neither bit performs its operation if the values written to the two bits are contradictory. when using instructions other than bit manipulation instructions (byte or larger instructions), only write the following bit combinations. when using a bit manipulation instruction (clear bit instruction), writing of the above combinations is enforced automatically by hardware so no particular care is required. (a) operation after starting ? timer mode: ...................... the count operation starts immediately. ? pulse width count mode: ... the count does not start until the count start edge is input. after detecting the count start edge, the 16-bit up-count timer is cleared to 0000 h and counting starts. (b) restarting the timer re-applying the start command (writing "0" to the strt bit) while the timer is still operating after start- ing in timer mode or pulse width count mode is called restarting. the operation performed for a restart depends on the mode, as follows. ? single-shot timer mode: .... no effect on the operation. ? reload timer mode:........... performs a reload and continues operation. if the restart occurs at the same time as an overflow, the overflow flag (ovir) is set and the pout bit inverted. ? pulse width count mode: ... has no effect on the operation if the timer is waiting for the count start edge. if applied during a count, the count halts and the timer returns to the "waiting for a count start edge" state. if the restart occurs at the same time as a count end edge is detected, the count end flag (edir) is set and, in continuous count mode, the count result is transferred to pwcr. (c) stopping the timer in single-shot timer mode or single-shot count mode, the count halts automatically when the timer overflows or the count ends and therefore you do not need to explicitly stop the timer. however, you must forcibly stop the timer in other modes or if you wish to stop the timer before it halts automatically. (d) checking the operating state the strt and stop bits described previously function as indicator bits for the operating state of the timer when read. the table below lists the bit meanings. the strt and stop bits both have the same value when read. however, as the bits always have the value "1 b " when read by read-modify-write instructions (such as bit manipulation instructions), do not use these instructions to read the bit values. table 18.4b start and stop bit functions function strt stop start or restart timer or pulse width count. 0 1 forcibly halt timer or pulse width count. 1 0 table 18.4c operating state indicator bit functions strt stop operating state 0 0 the timer is stopped (other than when waiting for a count start edge). indicates that the timer has not been started or that counting has ended. 1 1 the timer is counting or waiting for a count start edge. 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 257 (6) clearing the timer the 16-bit up-count timer is cleared to 0000 h in the following cases. ?a reset ? when counting starts after detection of a count start edge in pulse width count mode(6) (7) details of timer mode operation (a) single-shot operation mode when the timer is started in this mode, the timer counts up on each count clock. the timer automatically stops when an overflow from ffff h to 0000 h occurs. if pwcr is set before starting the timer, the count starts from the set value. in this case, the set value is not saved and pwcr contains the current count value. bit 8 (pout) of pwcsr is inverted when an overflow occurs but the value is not output from the pin in this mode, even if pulse output mode is specified. (b) reload operation mode when the timer is started in this mode, the reload value in pwcr is set to the timer and the timer counts up on each count clock. when an overflow from ffff h to 0000 h occurs, the reload value in pwcr is set again to the timer (reloading), the pout bit (bit 8) of pwcsr is inverted, and the count operation repeated. the timer does not stop until forcibly halted by writing to the stop bit of pwcsr or until a reset occurs. the reload value set to pwcr before starting the timer is stored during counting and is set to the timer when the timer is started or restarted and each time an overflow occurs. if the set value is changed during counting, the new reload value is used when the next overflow or restart occurs. (c) timer value and reload value in single-shot operation mode, accessing pwcr directly accesses the up-count timer. writing a value to pwcr writes the value directly to the timer and reading pwcr during count operation reads the current timer value. setting a value to pwcr before starting the timer causes the count to start from the specified value. in reload operation mode, the up-count timer cannot be accessed and pwcr acts as the reload register (stores the reload value). the value written to pwcr is set to the timer when the timer is started or restarted and each time an overflow occurs. reading pwcr reads the stored reload value. the value in pwcr and the timer value are indeterminate if the timer is set to single-shot mode after forcibly halting operation in reload mode. therefore, always set a value before using the timer. the value in pwcr is indeterminate if the timer is set to reload mode after forcibly halting operation in single-shot mode. therefore, always set a value before using the timer. (d) generation of interrupt requests interrupt requests can be generated by overflows when operating in timer mode. when an overflow occurs due to the timer counting up, the overflow flag is set and an interrupt request is generated if the overflow interrupt request is enabled. 18.4 operations 258 chapter 18: pulse width counter (pwc) timer MB90580 series (e) timer period if the timer is started in single-shot mode after setting 0000 h to pwcr, the timer overflows after 65536 counts and the count stops. the following formula calculates the time from the timer starting to the timer stopping. if the timer is started in reload mode after setting 0000 h to pwcr, the timer overflows after each 65536 counts. the following formulas calculate the reload period and the period of the pot pin output pulse. (f) count clock and maximum period for timer mode, the maximum period is when 0000 h is set to pwcr. the following table lists the count clock period and maximum timer period for a 16mhz machine cycle (indicated by f below). table 18.4d count clock and period count clock selection cks1, 0 = 00 ( f /4) cks1, 0 = 01 ( f /16) cks1, 0 = 10 ( f /32) count clock period 0.25s 1s 2s maximum timer period 16.38ms 65.5ms 131.1ms t 1 time from start to stop (s) t 1 = (65536 -n 1 ) t n 1 timer value set in pwcr when the timer starts t count clock period (s) ? ? ? t r reload period (overflow period) (s) t r = (65536 -n r ) t t pout period of the pot pin output pulse (s) t pout = t r 2 n r reload value stored in pwcr t count clock period (s) ? ? ? ? ? 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 259 (g) timer operation flowchart figure 18.4f flowchart of timer mode operation settings count clock selection operation and count mode selection clear interrupt flag enable interrupt set pulse output initial value set value to pwcr overflow occurs t set ovir flag invert pout bit value stop count stop operation restart start by strt bit reload operation mode single-shot operation mode reload pwcr value in timer start count up-count start count up-count overflow occurs t set ovir flag invert pout bit value 18.4 operations 260 chapter 18: pulse width counter (pwc) timer MB90580 series (8) details of pulse width count mode operation (a) count input pins and pin selection the pins used to input the signal for pulse width counting are fixed as pin pwc0 for ch0, pwc1 for ch1, pwc2 for ch2, and pwc3 for ch3. always set bits 4 and 5 of pwcsr to "00" on the MB90580. note: only select or change the count input pin while the timer is halted. (b) single-shot counting and continuous counting pulse width count mode has a mode to perform a count once only and a mode to perform pulse width counting continuously. the following lists the differences between the two modes. ? single-shot count mode: .. when the first count end edge is input, the timer stops counting, the count end flag (edir) in pwcsr is set, and no further count is per- formed. (however, if a restart is specified at the same time, the timer goes to the "waiting for a count start edge" state.) ? continuous count mode: ... when a count end edge is input, the timer stops counting, the count end flag (edir) in pwcsr is set, and the count remains stopped until the next count start edge is input. when the next count start edge is input, the timer is cleared to 0000 h and counting restarts. the count result in the timer is transferred to pwcr when the count ends. the s/c bit in pwcsr selects the mode (see (3) operation mode selection). note: only select or change the count mode while the timer is halted. note: for any of the pulse width count modes used with continuous count mode, the divider circuit for the internal count clock is not cleared when the count ends. therefore, the result in contin- uous count modes is the accumulated number of edges. (c) count result data the handling of the count result and timer value and the function of pwcr differ for single-shot count mode and continuous count mode. the differences are as follows. ? single-shot count mode: ... reading pwcr during timer operation reads the current timer value. reading pwcr after the count has ended reads the count result. ? continuous count mode: ... the count result in the timer is transferred to pwcr when the count ends. reading pwcr reads the result of the previous count. pwcr continues to store the previous count result while counting is in progress. the timer value during counting cannot be read. in continuous count mode, if the previous count result is not read before the next count completes, the new count result overwrites the old value. if this occurs, the error flag (err) in pwcsr is set. the error flag (err) is automatically cleared when pwcr is read. table 18.4e count input pin selection (n = 3 to 0) pis1 pis0 count input pin selection 0 0 the pwcn pin for the channel (initial value) 0 1 setting unavailable (do not set any of these values.) 10 11 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 261 (d) count mode and count operation the count mode can be selected from five different modes. the mode determines which part of the input pulse to measure. to accurately measure the width of high frequency pulses, a mode is available to divide the input pulses by a specified ratio and to measure the resulting period. the following describes each mode. table 18.4f count modes count mode mod2 mod1 mod0 count operation (w: pulse width being measured) h pulse width count 101 measures the width of the "h" period. ? count (meaopsurement) start: rising edge detected ? count (measurement) end: falling edge detected l pulse width count 110 measures the width of the "l" period. ? count (measurement) start: falling edge detected ? count (measurement) end: rising edge detected rising edge to rising edge period count 100 measures the time between rising edges. ? count (measurement) start: rising edge detected ? count (measurement) end: rising edge detected falling edge to falling edge period count 111 measures the time between falling edges ? count (measurement) start: falling edge detected ? count (measurement) end: falling edge detected w w y count start ? count stop y start ? stop w w ? count start y count stop ? start y stop w w y count start y count stop y stop w y start y stop y start w w ? count start ? count stop ? stop w ? start ? stop ? start 18.4 operations 262 chapter 18: pulse width counter (pwc) timer MB90580 series in all modes, the timer does not count during the time between starting the count and a count start edge being input. after the count start edge is input, the timer is cleared to 0000 h and the timer counts up on each count clock until a count end edge is input. the following operations are performed when a count end edge is input. (1) the count end flag (edir) in pwcsr is set. (2) the timer stops counting (unless the timer is restarted at the same time). (3) in continuous count mode:the timer value (count result) is transferred to pwcr and the count remains stopped until the next count start edge is input. (4) in single-shot count mode:the timer stops counting (unless the timer is restarted at the same time). in continuous count mode, the end edge also acts as the next start edge in some modes, including inter-edge pulse width count mode and period count mode. (e) minimum input pulse width pulses input to the pulse width count input pins (pwc3 to pwc0) must be longer than the minimum input pulse width shown below. pulse width:....... 2 machine cycles ( 3 0.125s for a 16mhz machine clock) however, input pulses shorter than the above specification may be recognized as valid pulses in some cases. the pwc inputs do not have a filter function in the MB90580 series. if required, use a filter or similar circuit externally. inter-edge pulse width count 010 measures the width between consecutive input edges. ? count (measurement) start: edge detected ? count (measurement) end: edge detected divided period count 011 the input pulses are divided by the divide ratio set in the divide ratio register (divr) and the resulting period measured. ? count (measurement) start: falling edge detected after operation started ? count (measurement) end: end of one period of the divided signal table 18.4f count modes (continued) count mode mod2 mod1 mod0 count operation (w: pulse width being measured) w w y count start ? count stop ? stop w ? start y stop y start w w w ? count start (divide by 4 example shown) y count stop y start ? stop 18.4 operations MB90580 series chapter 18: pulse width counter (pwc) timer 263 (f) pulse width/period calculation calculate the width or period of the measured pulse from the count result read from pwcr after the count ends as follows. (g) pulse width/period count range the range of pulse widths/periods that can be measured depends on the count clock and the divide ratio of the input divider. the table below lists the measurement range for a 16mhz machine cycle (indicated by f below). table 18.4g pulse width count range note: the figures in [ ] indicate the resolution per bit. (h) generation of interrupt requests the following two interrupt requests can be generated in pulse width count mode. (1) timer overflow interrupt request if an overflow occurs during counting, the overflow flag is set and, if the overflow interrupt request is enabled, an interrupt request is generated. (2) count end interrupt request when the count end edge is detected, the count end flag (edir) in pwcsr is set and, if the count end interrupt request is enabled, an interrupt request is generated. the count end flag (edir) is automatically cleared by reading pwcr. divide ratio div1.0 cks1, 0 = 00 ( f /4) cks1, 0 = 01 ( f /16) cks1, 0 = 10 ( f /32) no division C 0.125s to 16.38ms [0.25s] 0.125s to 65.5ms [1.6s] 0.2s to 131ms [3.2s] divide by 4 00 b 0.125s to 4.10ms [62.5s] 0.125s to 16.38ms [0.4s] 0.2s to 32.75ms [800ns] divide by 16 01 b 0.125s to 1024s [15.6ns] 0.125s to 4.10ms [0.1s] 0.2s to 8.19ms [200ns] divide by 64 10 b 0.125s to 256s [3.91ns] 0.125s to 1024s [25.0ns] 0.2s to 2.048ms [50.0ns] divide by 256 11 b 0.125s to 64s [0.98ns] 0.125s to 256s [6.25ns] 0.2s to 512ms [12.5ns] t w measured pulse width or period (s) n count result stored in pwcr t w = n t d iv (s) t count clock period (s) d iv divide ratio set in the divide ratio register (divr) (use the value 1 for modes other than divided period count mode.) ? ? ? ? ? ? ? 18.4 operations 264 chapter 18: pulse width counter (pwc) timer MB90580 series (i) flowchart of the pulse width count operation figure 18.4g flowchart of operation in pulse width count mode (9) initial state ? the initial values of each register are: pwcsr t (00000000 00000000) b pwcr t (00000000 00000000) b divr t (xxxxxx00) b settings count clock selection operation and count mode selection clear interrupt flag enable interrupt set pulse output initial value restart start by strt bit continuous count mode single-shot count mode count start edge detected start count up-count clear timer overflow occurs t set ovir flag count start edge detected start count up-count clear timer overflow occurs t set ovir flag count end edge detected t set edir flag stop count transfer timer value to pwcr count end edge detected t set edir flag stop count operation stops 18.5 precautions MB90580 series chapter 18: pulse width counter (pwc) timer 265 18.5 precautions (1) changing register values changing the values of the following pwcsr bits when the timer is operating is prohibited. only change bit values before starting the timer or after operation stops. [bits 7, 6] cks1, cks0: clock selection bits [bits 5, 4] pis1, pis0: count input pin selection bits [bit 3] s/c: count mode (single-shot or continuous) selection bit [bits 2, 1, 0] mod2, mod1, mod0: operating mode and count edge selection bits note that the value of the pulse output level indication bit (pout: bit 8) does not change if the bit is written to when the timer is operating. changing the divr value when the timer is operating is prohibited. only change the divr value before starting the timer or after operation stops. (2) count end flag in timer mode the value of the count end interrupt request flag (edir) in pwcsr has no meaning in timer mode. therefore, always set the enable bit for the count end interrupt request (edie) in pwcsr to "0". (3) strt and stop bits in pwcsr note that the meaning of these two bits differs depending on whether they are being read or written (see the register description for details). also note that read-modify-write instructions always read the bits as "11 b " regardless of the actual values. therefore, bit manipulation instructions cannot be used to read the operation state (as the result will always indicate "operating"). however, bit manipulation instructions (such as the bit clear instruction) can be used to write to the strt or stop bit to start or stop the timer. (4) clearing the timer in pulse width count mode, the timer is cleared by the count start edge and therefore the previous data in the timer has no meaning. (5) clock selection bits setting "11 b " to the clock selection bits (cks1, cks0: bits 7, 6) in pwcsr is prohibited. (6) pwcr and timer value when changing mode the value in pwcr and the timer value are indeterminate if the timer is set to single-shot mode after forc- ibly halting operation in reload mode. therefore, always set a value before using the timer. the value in pwcr is indeterminate if the timer is set to reload mode after forcibly halting operation in sin- gle-shot mode. therefore, always set a value before using the timer. when changing from pulse width count mode to timer mode, always set a value to pwcr before starting the timer. (7) minimum input pulse width the following restriction applies to pulses input to the pulse width count input pins. ? minimum input pulse width: machine cycle divided by 2 ( 3 0.125s for a 16mhz machine cycle) ? maximum input frequency: machine cycle divided by 4 ( 3 4mhz for a 16mhz machine cycle) the operation of the timer if pulses of shorter width or higher frequency are input is not guaranteed. if it is possible that such noise may be present on the input signal, use an external filter or similar circuit to suppress the noise. 18.5 precautions 266 chapter 18: pulse width counter (pwc) timer MB90580 series (8) divided period count mode note that the input pulses are divided when divided period count mode is used in pulse width count mode and therefore the pulse width calculated from the count result is an average value. (9) restarting the timer during operation depending on the timing, the following may occur when the timer is restarted after starting the count operation. (a) if the restart occurs at the same time as an overflow in reload timer mode: the timer restarts but the overflow flag (ovir) is set and the pout bit inverted. (that is, the same operations are performed as for a normal overflow.) (b) if the restart occurs at the same time as the count end edge in single-shot pulse width count mode: the timer restarts and waits for a count start edge but the count end flag (edir) is also set. (c) if the restart occurs at the same time as the count end edge in continuous pulse width count mode: the timer restarts and waits for a count start edge but the count end flag (edir) is also set and the count result at that time is transferred to pwcr. when restarting the timer while it is still operating, take note of the operation of the flags as described above and perform interrupt and other control accordingly. (10) pulse width count mode using continuous count mode note that, when performing continuous counting in this mode, the divider circuit for the internal count clock is not cleared and therefore the number of edges below the count clock is added to the result. chapter 19: clock monitor function 19.1 outline clock monitor function is used to output the machine clock to a port pin. this clock output is generated by dividing the machineclock by 2 1 to 2 8 . 19.2 block diagram figure 19.2a block diagram of clock monitor function f2mc-16lx bus cken frq2 frq1 frq0 clock division circuit machine clock p65/ckot 19.3 registers and register details 268 chapter 19: clock monitor function MB90580 series 19.3 registers and register details figure 19.3a registers of clock monitor function 19.3.1 clock output enable register (clkr) [bit 3] : cken ckot output enable bit. [bits 2, 1, and 0] frq2, frq1, and frq0 these bits are used to select the clock output frequency. 0 ordinary port 1 ckot output frq2 frq1 frq0 output clock ? =16 mhz ? =8 mhz ? =4 mhz 00 0 ? /2 1 125 ns 250 ns 500 ns 00 1 ? /2 2 250 ns 500 ns 1 m s 01 0 ? /2 3 500 ns 1 m s2 m s 01 1 ? /2 4 1 m s2 m s4 m s 10 0 ? /2 5 2 m s4 m s8 m s 10 1 ? /2 6 4 m s8 m s16 m s 11 0 ? /2 7 8 m s 16 m s32 m s 11 1 ? /2 8 16 m s 32 m s64 m s cken frq2 frq1 frq0 76543 2 10 address : 00003e h bit number clkr (-) (-) (-) (-) (0) (0) (0) (0) initial value (-) (-) (-) (-) (r/w) (r/w) (r/w) (r/w) read/write clock output enable register cken frq2 frq1 frq0 76543 2 10 address : 00003e h bit number clkr (-) (-) (-) (-) (0) (0) (0) (0) initial value (-) (-) (-) (-) (r/w) (r/w) (r/w) (r/w) read/write chapter 20: 16-bit i/o timer 20.1 outline the 16-bit i/o timer consists of a 16-bit free-run timer, two output compare modules, and four input capture modules. the count values of this timer are used as the base timer for output compare and input capture. using this function, two independent waveforms can be output based on 16-bit free-run timer to enable measurement of input pulse withs and external clock cycles. ? four types of counter clock are available. ? an interrupt can be generated upon a counter value overflow. ? the counter value can be initialized upon a match with compare register 0, depending on the mode. q 16-bit free-run timer ( 1) the 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. the 16-bit up counter is used to counting up in synchronization to the machine clock, in which an interrupt factor can be selected from the overflow interrupt and four types of timer intermediate bit interrupt to be operated as an interval timer. ? four types of counter clock are available. internal clock: ? /4, ? /16, ? /32, ? /64 ? an interrupt can be generated upon a counter value overflow or a match with compare register 0. (compare match can be used only in an appropriate mode.) ? the counter value can be initialized to '0000h' upon a reset, software clear, or match with compare register 0. the free-run timer can be used to generating reference timing signals for the input capture (icu) and output compare (ocu). q output compare ( 2) the output compare (ocu) consists of two 16-bit compare registers, compare output latch, and control register. an interrupt request can be generated for each channel upon a match detection by performing time-divi- sion comparison between the ocu compare data register setting value and the counter value of the 16-bit free-run timer. when the 16-bit free-run timer value matches the compare register value, the output level is reversed and an interrupt is issued. ? the four compare registers can be used independently. output pins and interrupt flags corresponding to compare registers ? output pins can be controlled based on pairs of the four compare registers. output pins can be reversed by using the four compare registers. ? initial values for output pins can be set. ? interrupts can be generated upon a compare match. 20.1 outline 270 chapter 20: 16-bit i/o timer MB90580 series q input capture ( 4) the input capture (icu) generates an interrupt request to the cpu simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the icu data register (ipcp) upon an input of a trigger edge to the external pin. there are four sets (four channels) of the input capture external pins and icu data registers (icdr), enabling measurements of maximum of four events. ? the input capture has four sets of external pins (in0 to in3) and icu registers (ipcp0~3), enabling measurements of maximum of four events. ? a trigger edge direction can be selected from rising/falling/both edges. ? the input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free-run counter to the icu data register (ipcp). ? the input compare conforms to the extended intelligent i/o service (ei 2 os). ? the input capture function is suited for measurements of intervals (frequencies) and pulse-widths. a reset clears the timer counter value for the 16-bit free-run timer to all zeroes. 20.2 block diagram MB90580 series chapter 20: 16-bit i/o timer 271 20.2 block diagram 20.2.1 overall block diagram of 16-bit i/o timer figure 20.2.1a overall block diagram of 16-bit i/o timer out0 t q t q out1 in2 in3 f 2 mc-16lx bus control logic interrupt 16-bit free-run timer 16-bit timer to each block clear output compare 0 compare register 0 output compare 1 compare register 1 input capture 3 capture register 2 capture register 3 edge selection edge selection in1 input capture 1 capture register 1 edge selection in0 input capture 0 capture register 0 edge selection input capture 4 20.2 block diagram 272 chapter 20: 16-bit i/o timer MB90580 series 20.2.2 block diagram of 16-bit free-run timer figure 20.2.2a block diagram of 16-bit free-run timer 20.2.3 block diagram of output comparison figure 20.2.3a block diagram of output comparison ivf ivfe stop mode clr clk1 clk0 t15 to t00 f 2 mc-16lx bus interrupt request comparator 0 divider 16-bit up counter clock count value output icp1 t q ote0 out0 cmod t q ote1 out1 icp0 ice1 ice0 16-bit timer counter value (t15 to t00) compare control 16-bit timer counter value (t15 to t00) compare control compare register 1 controller control blocks compare 1 interrupt compare 0 interrupt compare register 0 f 2 mc-16lx bus 20.2 block diagram MB90580 series chapter 20: 16-bit i/o timer 273 20.2.4 block diagram of input capture figure 20.2.4a block diagram of input capture eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 in0 (in2) in1 (in3) capture data register 0 16-bit timer counter value (t15 to t00) capture data register 1 edge detection interrupt 1 (3) interrupt 0 (2) edge detection f 2 mc-16lx bus 20.3 registers and register details 274 chapter 20: 16-bit i/o timer MB90580 series 20.3 registers and register details 20.3.1 16-bit free-run timer figure 20.3.1a registers of 16-bit free-run timer 15 14 13 12 11 10 9 8 r/w 0 address: 00006d h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 bit number address: 00006c h t07 t06 t05 t04 t03 t02 t01 t00 76543 2 10 16-bit timer data register (upper) 16-bit timer data register (lower) r/w 0 address: 00006e h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 reserved ivf ivfe stop mode clr clk1 clk0 bit 76543 2 10 16-bit timer control status register tcdth tcdtl tccs initial value read/write initial value read/write bit number bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write 20.3 registers and register details MB90580 series chapter 20: 16-bit i/o timer 275 20.3.1.1 16-bit free-run timer data register the data register can read the count value of the 16-bit free-run timer. the counter value is cleared to '0000' upon a reset. the timer value can be set by writing a value to this register. however, ensure that the value is written while the operation is stopped (stop=1). the data register must be accessed in word access mode. the 16-bit free-run timer is initialized upon the following factors: ? reset ? clear bit (clr) of control status register ? a match between compare register 0 and the timer counter value (this can be performed only in an appropriate mode.) 15 14 13 12 11 10 9 8 r/w 0 address: 00006d h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 bit number address: 00006c h t07 t06 t05 t04 t03 t02 t01 t00 76543 2 10 16-bit timer data register (upper) 16-bit timer data register (lower) tcdth tcdtl initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write 20.3 registers and register details 276 chapter 20: 16-bit i/o timer MB90580 series 20.3.1.2 16-bit free-run timer control status register [bit 7] reserved bit always write '0' to this bit. [bit 6] ivf this bit is an interrupt request flag of the 16-bit free-run timer. if the 16-bit free-run timer overflows, or if the counter is cleared by a match with compare register 0 in a certain mode, '1' is written to this bit. an interrupt is issued if the interrupt request enable bit (bit 5: ivfe) is set. this bit is cleared by writing '0.' writing '1' has no effect. '1' is always read by a read-modify-write instruction. [bit 5] ivfe ivfe is an interrupt enable bit of the 16-bit free-run timer. while '1' is written to this bit, an interrupt is issued if '1' is written to the interrupt flag (bit 5: ivf). [bit 4] stop the stop bit is used to stop the 16-bit free-run timer. writing '1' to this bit stops the timer. writing '0' starts the timer. * the output compare operation stops when the 16-bit free-run timer stops. 0 no interrupt request (default) 1 interrupt request 0 interrupt disabled (default) 1 interrupt enabled 0 counting enabled (operation) (default) 1 counting disabled (stop) r/w 0 address: 00006e h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 reserved ivf ivfe stop mode clr clk1 clk0 bit 76543 2 10 16-bit timer control status register tccs initial value read/write bit number 20.3 registers and register details MB90580 series chapter 20: 16-bit i/o timer 277 [bit 3] mode the mode bit is used to set the initialization condition of the 16-bit free-run timer. when '0' is set, the counter value can be initialized by a reset or a clear bit (bit 2: clr). when '1' is set, the counter value can be initialized by a match with compare register 0 in addition to a reset and a clear bit (bit 2: clr). * the counter value is initialized where the count value is changed. [bit 2] clr the clr bit initializes the operating 16-bit free-run timer value to '0000.' when '1' is set, the counter value is initialized to '0000.' writing '0' has no effect. '0' is always read from this bit. the counter value is initialized where the count value changes. * to initialize the counter value while the timer is stopped, write '0000' to the data register. [bits 1 and 0] clk1 and clk0 clk1 and clk0 are used to select the count clock for the 16-bit free-run timer. the clock is updated immediately after a value is written to these bits. therefore, ensure that the output compare and input capture operations are stopped before a value is written to these bits. * ? = machine clock 0 initialization by reset or clear bit (default) 1 initialization by reset, clear bit, or compare register 0 0 no effect (default) 1 the counter value is initialized to '0000. clk1 clk0 count clock ? =16 mhz ? =8 mhz ? =4 mhz ? =1 mhz 00 ? /4 0.25 m s0.5 m s1 m s4 m s 01 ? /16 1 m s2 m s4 m s16 m s 10 ? /64 4 m s8 m s 16 m s64 m s 11 ? /256 16 m s32 m s 64 m s256 m s 20.3 registers and register details 278 chapter 20: 16-bit i/o timer MB90580 series 20.3.2 output comparison the output compare module consists of 16-bit compare registers, compare output pins, and control regis- ter. if the value written to the compare register of this module matches the 16-bit free-run timer value, the output level of the pin can be reversed and an interrupt can be issued. ? two compare registers exist that can be used independently. depending on the setting, the two com- pare registers can be used to control pin outputs. ? the initial value for the pin output can be specified. ? an interrupt can be issued upon a match as a result of comparison. figure 20.3.2a registers of output comparsion address: 00005b h 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x c15 c14 c13 c12 c11 c10 c09 c08 c07 c06 c05 c04 c03 c02 c01 c00 76543 2 10 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 15 14 13 12 11 10 9 8 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 76543 2 10 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 00005d h occp0 (upper) occp1 (upper) initial value read/write address: 00005a h 00005c h occp0 (lower) occp1 (lower) output compare register 0, 1 output compare control status register 0, 1 address: 00005f h address: 00005e h ocs1 ocs0 bit number initial value read/write bit number bit number initial value read/write initial value read/write bit number 20.3 registers and register details MB90580 series chapter 20: 16-bit i/o timer 279 20.3.2.1 compare register this 16-bit compare register is compared with the 16-bit free-run timer. since the initial register value is undefined, set a value before enabling the register. this register must be accessed in word mode. when the value of this register matches that of the 16-bit free-run timer, a compare signal is generated and the output compare interrupt flag is set. if output is enabled, the output level corresponding to the compare register is reversed. address: 00005b h 15 14 13 12 11 10 9 8 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x c15 c14 c13 c12 c11 c10 c09 c08 c07 c06 c05 c04 c03 c02 c01 c00 76543 2 10 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x 00005d h occp0 (upper) occp1 (upper) initial value read/write address: 00005a h 00005c h occp0 (lower) occp1 (lower) output compare register 0, 1 bit number initial value read/write bit number 20.3 registers and register details 280 chapter 20: 16-bit i/o timer MB90580 series 20.3.2.2 control status register [bits 15, 14, and 13] unused bits [bit 12] cmod cmod is used to switch the pin output level reverse mode upon a match while pin output is enabled (ote1=1 or ote0=1). ? when cmod=0 (default), the output level of the pin corresponding to the compare register is reversed. out0: the level is reversed upon a match with compare register 0. out1: the level is reversed upon a match with compare register 1. ? when cmod=1, the output level is reversed for compare register 0 in the same manner as for cmod=0. the output level of the pin corresponding to compare register 1 (out1), however, is reversed upon a match with compare register 0 or 1. if compare registers 0 and 1 have the same value, the same operation as with a single compare register is performed. out0: the level is reversed upon a match with compare register 0. out1: the level is reversed upon a match with compare register 0 or 1. [bits 11 and 10] ote1 and ote0 these bits are used to enable output compare pin output. the initial value for these bits is '0.' * ote1: corresponds to output compare 1/3 ote0: corresponds to output compare 0/2 * out0/1 are multiplexed with p94/tout1 and p95/tout2 respectively. whne both output capture and reload timer output are enabled. out0/out1 get the higher priority. [bits 9 and 8] otd1 and otd0 these bits are used to change the pin output level when the output compare pin output is enabled. the initial value of the compare pin output is '0.' ensure that the compare operation is stopped before a value is written. when read, these bits indicate the output compare pin output value. * otd1: corresponds to output compare 1/3 otd0: corresponds to output compare 0/2 0 general-purpose port (default) 1 output compare pin output 0 sets '0' for the compare pin output. (default) 1 sets '1' for the compare pin output. 15 14 13 12 11 10 9 8 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 cmod ote1 ote0 otd1 otd0 icp1 icp0 ice1 ice0 cst1 cst0 76543 2 10 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 output compare control status register 0, 1 address: 00005f h address: 00005e h ocs1 ocs0 bit number initial value read/write initial value read/write bit number 20.3 registers and register details MB90580 series chapter 20: 16-bit i/o timer 281 [bits 7 and 6] icp1 and icp0 these bits are used as output compare interrupt flags. '1' is written to these bits when the compare reg- ister value matches the 16-bit free-run timer value. while the interrupt request bits (ice1 and ice0) are enabled, an output compare interrupt occurs when the icp1 and icp0 bits are set. these bits are cleared by writing '0.' writing '1' has no effect. '1' is always read by a read-modify-write instruction. * icp1: corresponds to output compare 1/3 icp0: corresponds to output compare 0/2 [bits 5 and 4] ice1 and ice0 these bits are used as output compare interrupt enable flags. while the '1' is written to these bits, an output compare interrupt occurs when an interrupt flag (icp1 or icp0) is set. * ice1: corresponds to output compare 1/3 ice0: corresponds to output compare 0/2 [bits 3 and 2] unused bits [bits 1 and 0] cst1 and cst0 the*se bits are used to enable the comparison with 16-bit free-run timer. ensure that a value is written to the compare register before the compare operation is enabled. * cst1: corresponds to output compare 1/3 cst0: corresponds to output compare 0/2 note: since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. 0 no compare match (default) 1 compare match 0 output compare interrupt disabled (default) 1 output compare interrupt enabled 0 compare operation disabled (default) 1 compare operation enabled 20.3 registers and register details 282 chapter 20: 16-bit i/o timer MB90580 series 20.3.3 input capture this module detects a rising or falling edge or both edges of an externally input signal and stores the 16-bit free-run timer value in a register. in addition, this module can generate an interrupt upon detection of an edge. the input capture module consists of an input capture data register and a control register. each input capture has a corresponding external input pin. ? the detection edge of an external input can be selected from three types. ? rising edge, falling edge, or both edges ? an interrupt can be generated upon detection of a valid edge of an external input. figure 20.3.3a register of input capture 15 14 13 12 11 10 9 8 r address: 000061 h 76543 2 10 cp12 cp11 cp09 cp08 cp12 cp13 cp15 cp14 cp03 cp02 cp01 cp00 cp04 cp05 cp07 cp06 x r x r x r x r x r x r x r x r x r x r x r x r x r x r x r x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 765432 10 000063 h 000065 h 000067 h address: 000060 h 000062 h 000064 h 000066 h ipcp0 (upper) ipcp1 (upper) ipcp2 (upper) ipcp3 (upper) ipcp0 (lower) ipcp1 (lower) ipcp2 (lower) ipcp3 (lowerr) address: 000068 h 00006a h ics01 ics23 input capture data register 0, 1, 2, 3 input capture control status register ch0,1 & ch2,3 initial value read/write bit number initial value read/write bit number initial value read/write bit number 20.3 registers and register details MB90580 series chapter 20: 16-bit i/o timer 283 20.3.3.1 input capture data register this register stores the 16-bit timer value when a valid edge of the corresponding external pin input wave- form is detected. (this register must be accessed in word mode. no value can be written to this register.) 15 14 13 12 11 10 9 8 r address: 000061 h 76543 2 10 cp12 cp11 cp09 cp08 cp12 cp13 cp15 cp14 cp03 cp02 cp01 cp00 cp04 cp05 cp07 cp06 x r x r x r x r x r x r x r x r x r x r x r x r x r x r x r x 000063 h 000065 h 000067 h address: 000060 h 000062 h 000064 h 000066 h ipcp0 (upper) ipcp1 (upper) ipcp2 (upper) ipcp3 (upper) ipcp0 (lower) ipcp1 (lower) ipcp2 (lower) ipcp3 (lowerr) input capture data register 0, 1, 2, 3 initial value read/write bit number initial value read/write bit number 20.3 registers and register details 284 chapter 20: 16-bit i/o timer MB90580 series 20.3.3.2 control status register [bits 7 and 6] icp1 and icp0 these bits are used as input capture interrupt flags. '1' is written to this bit upon detection of a valid edge of an external input pin. while the interrupt enable bits (ice0 and ice1) are set, an interrupt can be generated upon detection of a valid edge. these bits are cleared by writing '0.' writing '0' has no effect. '1' is always read by a read-modify-write instruction. * icp0: corresponds to input capture 0. icp1: corresponds to input capture 1. [bits 5 and 4] ice1 and ice0 these bits are used to enable input capture interrupts. while '1' is written to these bits, an input capture interrupt is generated when the interrupt flag (icp0 or icp1) is set. * ice0: corresponds to input capture 0. ice1: corresponds to input capture 1. [bits 3, 2, 1, and 0] eg11, eg10, eg01, and eg00 these bits are used to specify the valid edge polarity of an external input. these bits are also used to enable input capture operation. *eg01 and eg00: correspond to input capture 0. eg11 and eg10: correspond to input capture 1. 0 no valid edge detection (default) 1 valid edge detection 0 interrupt disabled (default) 1 interrupt enabled eg11 eg01 eg10 eg00 edge detection polarity 0 0 no edge detection (stop) 0 1 rising edge detection 1 0 falling edge detection 1 1 both edge detection r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 765432 10 address: 000068 h 00006a h ics01 ics23 input capture control status register ch0,1 & ch2,3 initial value read/write bit number (default) 20.4 operations MB90580 series chapter 20: 16-bit i/o timer 285 20.4 operations 20.4.1 16-bit free-run timer the 16-bit free-run timer starts counting from counter value '0000' after the reset is released. the counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations. the counter value is cleared in the following conditions: ? when an overflow occurs. ? when a match with output compare register 0 occurs. (this depends on the mode.) ? when '1' is written to the clr bit of the tccs register during operation. ? when '0000' is written to the tcdc register during stop. ? reset an interrupt can be generated when an overflow occurs or when the counter is cleared due to a match with compare register 0. (compare match interrupts can be used only in an appropriate mode.) n clearing the counter by an overflow n clearing the counter upon a match with output compare register 0 ffff h bfff h 7fff h 3fff h 0000 h counter value overflow time reset interrupt ffff h bfff h 7fff h 3fff h 0000 h bfff h counter value match time reset compare interrupt match register value 20.4 operations 286 chapter 20: 16-bit i/o timer MB90580 series 20.4.2 16-bit output compare in 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. n sample output waveform when compare registers 0 and 1 are used (the initial output value is 0.) the output level can be changed using two compare registers (when cmod=1). n sample output waveform with two compare registers (the initial output value is '0.') ffff h bfff h 7fff h 3fff h 0000 h out0 out1 bfff h 7fff h counter value time reset compare register 0 compare register 1 compare 0 compare 1 value value interrupt interrupt ffff h bfff h 7fff h 3fff h 0000 h out0 out1 bfff h 7fff h counter value time reset compare register 0 compare register 1 corresponds to compare 0 compare 1 value value compare 0 and 1 interrupt interrupt 20.4 operations MB90580 series chapter 20: 16-bit i/o timer 287 20.4.3 16-bit input capture in 16-bit input capture operation, an interrupt can be generated upon detection of a specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register. n sample input capture fetch timing capture 0: rising edge capture 1: falling edge capture example: both edges ffff h bfff h 7fff h 3fff h 0000 h in1 in0 3fff h bfff h 7fff h 7fff h counter value time reset capture 0 capture 1 capture capture 0 capture 1 capture example in example interrupt interrupt interrupt undefined undefined undefined 20.5 timing 288 chapter 20: 16-bit i/o timer MB90580 series 20.5 timing 20.5.1 16-bit free-run timer count timing the 16-bit free-run timer is incremented based on the input clock (internal or external clock). when exter- nal clock is selected, the 16-bit free-run timer is incremented at the rising edge. n free-run timer count timing the counter can be cleared upon a reset, software clear, or a match with compare register 0. by a reset or software clear, the counter is immediately cleared. by a match with compare register 0, the counter is cleared in synchronization with the count timing. n free-run timer clear timing (match with compare register 0) n n+1 counter value external clock count clock input n n 0000h compare register value compare match counter value 20.5 timing MB90580 series chapter 20: 16-bit i/o timer 289 20.5.2 output compare timing in output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. the output value can be reversed and an interrupt can be issued. the output reverse timing upon a compare match is synchronized with the counter count timing. n compare operation upon update of compare register when the compare register is updated, comparison with the counter value is not performed. n interrupt timing n output pin change timing n m n+1 n+2 n+3 m n+1 n+3 counter value no match signal is generated. compare register 0 value compare 0 stop compare 1 stop compare register 0 write compare register 1 value compare register 1 write n n n+1 counter value compare register compare match interrupt value n n+1 n n n+1 counter value compare register compare match pin output value signal 20.5 timing 290 chapter 20: 16-bit i/o timer MB90580 series 20.5.3 input capture input timing n capture timing for input signals n n+1 n+1 counter value input capture capture signal capture register interrupt valid edge input chapter 21: rom correction module 21.1 outline when the setting of the address is the same as the rom correction address register, the int9 instruction will be executed. by processing the int9 interrupt service routine, the rom correction function can be achieved. there are two address registers, in each containing compare enable bit. when the address register and the program counter are in agreement, and when the compare enable bit is at 1, then the cpu will be forced to execute int9 instruction. 21.2 block diagram figure 21.2a block diagram of rom correction module address latch rom correction address register enable bit f 2 mc-16 lx cpu core int9 command comparitor f2mc-16lx bus 21.3 registers and register details 292 chapter 21: rom correction module MB90580 series 21.3 registers and register details figure 21.3a registers of rom correction module 21.3.1 program address detect register 0/1 (padr0/padr1) these registers hold the addresses for the comparison with program counter. if there is an agreement and when the corresponding adcsr interrupt enable bit is at 1, this module demands the cpu to execute the int9 instruction. if the corresponding interrupt enalble bit is 0, nothing will occur even there is a match. the correspondance to the pacsr will be as follows. ad1e ad0e 76543 2 10 address : 009e h pacsr (C) (C) (0) (0) (0) (0) (0) (0) initial value bit number (C) (C) (C) (C) (r/w) (C) (r/w) (C) read/write padr0 1ff2h/1ff1h/1ff0h padr1 1ff5h/1ff4h/1ff3h byte byte byte access initial value r/w r/w undefined undefined program address detect control status register program address detect register 0/1 padr0 1ff2h/1ff1h/1ff0h padr1 1ff5h/1ff4h/1ff3h byte byte byte access initial value r/w r/w undefined undefined program address detect register 0/1 padr0 padr1 ad0e ad1e compare enable bit rom correction register 21.3 registers and register details MB90580 series chapter 21: rom correction module 293 21.3.2 program address detect control status register (pacsr) this register provides control bits and status bit for the rom correction function. [bit 5~4] these are the reserved bits, be sure to write 0. [bit 3]: ad1e (compare enable 1) this is the adr1 enable bit. when this bit is at 1, this module compares the padr1 register and the program counter. if there is an agreement, the int9 instruction is sent to the cpu. [bit 2]: this is a reserved bit. [bit 1]: ad0e (compare enable 0) this is the adr0 enable bit. when this bit is at 1, this module compares the padr0 register and the program counter. if there is an agreement, the int9 instruction is sent to the cpu. [bit 0]: this is a reserved bit. ad1e ad0e 76543 2 10 address : 009e h pacsr (C) (C) (0) (0) (0) (0) (0) (0) initial value bit number (C) (C) (C) (C) (r/w) (C) (r/w) (C) read/write program address detect control status register 21.4 operations 294 chapter 21: rom correction module MB90580 series 21.4 operations when the program counter indicates the same address as the rom correction address register, the int9 instruction will be executed. by processing the int9 interrupt service routine, the rom correction function can be achieved. there are two address registers, in each containing a compare enable bit. when the address register and the program counter are in agreement, and when the compare enable bit is at 1 , then the cpu will be forced to execute int9 instructions. note: when the address detection register and the program counter are in agreement, the internal data bus content will be forced to be 01h, so interrupt int9 will be executed. before changing the content of the address detect register, make sure the compare enable bit is at 0. if it is changed while the compare enable bit is at 1, there will occur an error. 21.5 application example MB90580 series chapter 21: rom correction module 295 21.5 application example (1) system structure figure 21.5a system structure example (2) eprom memory map address:content 0000h:number of bytes of the corrected program no. 0 (0 implies no rom correction) 0001h:bit 7-0 program address no. 0 0002h:bit 15-8 program address no. 0 0003h:bit 24-16 program address no. 0 0004h:number of bytes of the corrected program no. 0 (0 implies no rom correction) 0005h:bit 7-0 program address no. 1 0006h:bit 15-8 program address no. 1 0007h:bit 24-16 program address no. 1 0010h~: corrected program no. 0/1 body (3) initial condition eprom all at 0. (4) when rom correction is needed send the body of the corrected program and the program address to the mcu through the connector (uart). mcu will write that information into the eeprom. (5) reset sequence after resetting, the mcu reads the content of the eeprom. if the byte number of the corrected program is not 0, the body of the corrected program will be read from the eeprom and written in the ram. then the mcu sets the correction address either on padr0 or on padr1 and sets the compare enable bit. first address of the corrected program can be written in the user-defined location of the ram if a relocat- able correction program is desired. in this case int9 service routine looks for this user-defined location to jump to the corrected program. mcu f2mc16-lx sin eprom pull up resistor connector (uart) 21.5 application example 296 chapter 21: rom correction module MB90580 series (6) int9 interrupt in the interrupt routine, the address that produces the interrupt can be known by checking the stack program couter value. the information stacked during interrupt will be discarded. figure 21.5b rom correction processing example ffffffh 000000h MB90580 rom ram o number of program byte o interrupt trigger address o corrected program corrected program erroneous program data sent via uart external e 2 prom register setting for rom correction (3) pc= trigger address (1) (2) 21.5 application example MB90580 series chapter 21: rom correction module 297 figure 21.5c rom correction processing flow diagram reset read the 00h of e 2 prom 0000h (e2prom)=0 read the address 0001h~0003h (e2prom) mov padr0 (mcu) read the corrected program 0010h~0090h (e2prom) mov 000400h~000480h (mcu) enable compare mov pacsr, #02h to corrected program jmp 000400h corrected program execution 000400h~000480h end of corrected program jmp ff0050h int9 int9 normal program execution pc=padr0 no no yes yes corrected program size of corrected upper program address: ff middle program address: 00 lower program address: 00 e 2 prom ffff h 0090 h 0010 h 0003 h 0002 h 0001 h 0000 h i/o area ram/register area ram area stack area ffffff h ff0050 h ff0000 h fe0000 h 001100 h 000480 h 000400 h 000100 h 000000 h rom ram erroneous program corrected program program in byte: 80 chapter 22: rom mirroring module 22.1 outline in rom mirroring module the ff bank of the rom can be seen through the 00 bank when chosen during register setting. 22.2 block diagram figure 22.2a block diagram of rom mirroring module rom mirrroring register rom 00 bank ff bank address area f 2 mc-16lx bus 22.3 registers and register details 300 chapter 22: rom mirroring module MB90580 series 22.3 registers and register details figure 22.3a register of rom mirroring module 22.3.1 rom mirror function select register note: do not access this register when the addresses 004000 h ~00ffff h is being accessed. [bit 8] : mi the rom data in the ff bank can also be found in the 00 bank when 1 is written to this bit. however, such as memory mapping will not be done when this bit is written to 0. this bit is write only. the memory during single chip mode and during internal rom external bus mode will be as shown below. note: only ff4000~ffffff is mirrorred to 004000~00ffff when rom mirroring functing is activated. therefore, addresses fff000~ff3fff will not be mirrorred to 00 bank. mb90583 mb90f583 mb90v580 address 1 fe0000 h fe0000 h fe0000 h address 2 001900 h 001900 h 001900 h mi 15 14 13 12 11 10 98 address : 0006f h romm (C) (C) (C) (C) (C) (C) (C) (1) initial value bit number (C) (C) (C) (C) (C) (C) (w) read/write rom mirror function select register (C) mi 15 14 13 12 11 10 98 address : 0006f h romm (C) (C) (C) (C) (C) (C) (C) (1) initial value bit number (C) (C) (C) (C) (C) (C) (w) read/write rom mirror function select register (C) 22.3 registers and register details MB90580 series chapter 22: rom mirroring module 301 figure 22.3b memory in single chip mode figure 22.3c memory in internal rom external bus mode rom area rom area ram area io area io area ram area rom area ffffff h address 1 010000 h 004000 h 002000 h address 2 000100 h 0000c0 h 000000 h address internal area when mi= 1 when mi= 0 rom area rom area ram area io area rom area ram area io area ffffff h address 1 010000 h 004000 h 002000 h address 2 000100 h 0000c0 h 000000 h address when mi= 1 when mi= 0 internal area external bus area appendix a: i/o map a.1 i/o map table a.1a lists the addresses assigned to the registers of each microcontroller resource table a.1a i/o map address register abbreviation access resource initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx 06 h port 6 data register pdr6 r/w port 6 --xxxxxx 07 h port 7 data register pdr7 r/w port 7 ---xxxx- 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx 0a h port a data register pdra r/w port a -----xxx 0b to 0f h reserved area 10 h port 0 direction register ddr0 r/w port 0 00000000 11 h port 1 direction register ddr1 r/w port 1 00000000 12 h port 2 direction register ddr2 r/w port 2 00000000 13 h port 3 direction register ddr3 r/w port 3 00000000 14 h port 4 direction register ddr4 r/w port 4 00000000 15 h port 5 direction register ddr5 r/w port 5 00000000 16 h port 6 direction register ddr6 r/w port 6 --000000 17 h port 7 direction register ddr7 r/w port 7 ---0000- 18 h port 8 direction register ddr8 r/w port 8 00000000 19 h port 9 direction register ddr9 r/w port 9 00000000 1a h port a direction register ddra r/w port a -----000 1b h port 4 pin register odr4 r/w port 4 00000000 1c h analog input enable register ader r/w port 5, a/d 11111111 1d to 1f h reserved area 20 h serial mode register 0 smr0 r/w uart0 00000000 21 h serial control register 0 scr0 r/w 00000100 22 h serial input register/serial output register 0 sidr/ sodr0 r/w xxxxxxxx 23 h serial status register 0 ssr0 r/w 00001-00 24 h serial mode register 1 smr1 r/w uart1 00000000 25 h serial control register 1 scr1 r/w 00000100 26 h serial input register/serial output register 1 sidr/ sodr1 r/w xxxxxxxx 27 h serial status register 1 ssr1 r/w 00001-00 28 h serial mode register 2 smr2 r/w uart2 00000000 29 h serial control register 2 scr2 r/w 00000100 2a h serial input register/serial output register 2 sidr/ sodr2 r/w xxxxxxxx 2b h serial status register 2 ssr2 r/w 00001-00 a.1 i/o map 304 appendix a: i/o map MB90580 series 2c h clock division control register 0 cdcr0 r/w communication prescaler 0 0---1111 2d h reserved area 2e h clock division control register 1 cdcr1 r/w communication prescaler 1 0---1111 2f h reserved area 30 h interrupt /dtp enable register enir r/w dtp/external interrupt 00000000 31 h interrupt/dtp cause register eirr r/w xxxxxxxx 32 h request level setting register elvr r/w 00000000 33 h 00000000 34 h clock division control register 2 cdcr2 r/w communication prescaler 2 0---1111 35 h reserved area 36 h control status register adcs1 r/w a/d converter 00000000 37 h adcs2 00000000 38 h data register adcr1 r xxxxxxxx 39 h adcr2 00001--xx 3a h d/a converter data register 0 dat0 r/w d/a converter xxxxxxxx 3b h d/a converter data register 1 dat1 r/w xxxxxxxx 3c h d/a control register 0 dacr0 r/w - - - - - - - 0 3d h d/a control register 1 dacr1 r/w - - - - - - - 0 3e h clock output enable register clkr r/w clock monitor function - - - - 0000 3f h reserved area 40 h reload register l (ch.0) prll0 r/w 8-/16-bit ppg xxxxxxxx 41 h reload register h (ch.0) prlh0 r/w xxxxxxxx 42 h reload register l (ch.1) prll1 r/w xxxxxxxx 43 h reload register h (ch.1) prlh1 r/w xxxxxxxx 44 h ppg0 operation mode control register ppgc0 r/w 0x000xx1 45 h ppg1 operation mode control register ppgc1 r/w 0x000001 46 h ppg0 and ppg1 output control register ppgoe r/w 00000000 47 h reserved area 48 h control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 49 h ---- 0000 4a h 16-bit timer register 0 / 16-bt reload register 0 tmr0 / tmrlr0 r/w xxxxxxxx 4b h xxxxxxxx 4c h control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 4d h ---- 0000 4e h 16-bit timer register 1 / 16-bt reload register 1 tmr1 / tmrlr1 r/w xxxxxxxx 4f h xxxxxxxx 50 h control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 51 h ---- 0000 52 h 16-bit timer register 2 / 16-bt reload register 2 tmr2 / tmrlr2 r/w xxxxxxxx 53 h xxxxxxxx 54 h pwc control status register pwcsr r/w 16-bit pwc timer 00000000 55 h 00000000 56 h pwc data buffer register pwcr r/w xxxxxxxx 57 h xxxxxxxx 58 h divide ratio control register divr r/w ------00 59 h reserved area table a.1a i/o map (continued) address register abbreviation access resource initial value a.1 i/o map MB90580 series appendix a: i/o map 305 5a h output compare register 0 occp0 r/w output compare (channel 0 to 1) xxxxxxxx 5b h xxxxxxxx 5c h output compare register 1 occp1 r/w xxxxxxxx 5d h xxxxxxxx 5e h output compare control status register 0 ocs0 r/w 0000--00 5f h output compare control status register 1 ocs1 r/w ---00000 60 h input capture register 0 ipcp0 r input capture (channel 0 to 3) xxxxxxxx 61 h r xxxxxxxx 62 h input capture register 1 ipcp1 r xxxxxxxx 63 h r xxxxxxxx 64 h input capture register 2 ipcp2 r xxxxxxxx 65 h r xxxxxxxx 66 h input capture register 3 ipcp3 r xxxxxxxx 67 h r xxxxxxxx 68 h input capture control status register ch0,1 ics01 r/w 00000000 69 h reserved area 6a h input capture control status register ch2,3 ics23 r/w 00000000 6b h reserved area 6c h 16-bit timer data register (low) tcdtl r/w free run timer 00000000 6d h 16-bit timer data register (high) tcdth r/w 00000000 6e h 16-bit timer control status register tccs r/w 00000000 6f h rom mirror function select register romm w rom mirroring module ---- ---1 70 h unit address register (low) mawl r/w iebus interface xxxxxxxx 71 h unit address register (high) mawh r/w xxxxxxxx 72 h slave address register (low) sawl r/w xxxxxxxx 73 h slave address register (high) sawh r/w xxxxxxxx 74 h telegraph length set register dewr r/w 00000000 75 h multiaddress, control bit set register dcwr r/w 00000000 76 h command register (low) cmrl r/w xx00000 77 h command register (high) cmrh r/w 000000xx 78 h status register (low) strl r 0011xxxx 79 h status register (high) strh r/w 00000000 7a h lock read register (low) lrrl r xxxxxxxx 7b h lock read register (high) lrrh r xxx0xxxx 7c h master address read register (low) marl r xxxxxxxx 7d h master address read register (high) marh r xxxxxxxx 7e h telegraph length read register derr r xxxxxxxx 7f h multiaddress, control bit read register dcrr r 000xxxxx 80 h write data buffer wdb r/w xxxxxxxx 81 h read data buffer rdb r xxxxxxxx 82 h serial mode register 3 smr3 r/w uart3 00000000 83 h serial control register 3 scr3 r/w 00000100 84 h serial input register/serial output register 3 sidr/ sodr3 r/w xxxxxxxx 85 h serial status register 3 ssr3 r/w 00001-00 86 h pwc noise cancelling register rncr r/w pwc noise filter ---- -000 87 h clock division control register 3 cdcr3 r/w communication prescaler 3 0---1111 table a.1a i/o map (continued) address register abbreviation access resource initial value a.1 i/o map 306 appendix a: i/o map MB90580 series 88 h serial mode register 4 smr4 r/w uart4 00000000 89 h serial control register 4 scr4 r/w 00000100 8a h serial input register/serial output register 4 sidr/ sodr4 r/w xxxxxxxx 8b h serial status register 4 ssr4 r/w 00001-00 8c h port 0 resistor register rdr0 r/w port 0 00000000 8d h port 1 resistor register rdr1 r/w port 1 00000000 8e h port 6 resistor register rdr6 r/w port 6 --000000 8f h clock division control register 4 cdcr4 r/w communication prescaler 4 0---1111 90 h to 9d h reserved area 9e h program address detect control status register pacsr r/w rom correction module --000000 9f h delayed interrupt cause occurrence/ release register dirr r/w delayed interrupt occurrence module - - - - - - -0 a0 h low-power mode register lpmcr r/w low power 00011000 a1 h clock selection register ckscr r/w 11111100 a2 h low noise output select register (lower) lnsrl r/w i/o port 00000000 a3 h low noise output select register (upper) lnsrh r/w i/o port ----0000 a4 h reserved area a5 h automatic read function selection register arsr w external bus interface 0011- -00 a6 h external address output control register hacr w 0000000 a7 h bus control signal selection register ecsr w 0000000- a8 h watchdog control register wdtc r/w watchdog timer xxxxx111 a9 h time base timer control register tbtc r/w time base timer 1- -00100 aa h watch timer control register wtc r/w watch timer 1x000000 ab h to ad h reserved area ae h flash control register fmcs r/w flash interface 000x0xx0 af h reserved area b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 b1 h interrupt control register 01 icr01 r/w 00000111 b2 h interrupt control register 02 icr02 r/w 00000111 b3 h interrupt control register 03 icr03 r/w 00000111 b4 h interrupt control register 04 icr04 r/w 00000111 b5 h interrupt control register 05 icr05 r/w 00000111 b6 h interrupt control register 06 icr06 r/w 00000111 b7 h interrupt control register 07 icr07 r/w 00000111 b8 h interrupt control register 08 icr08 r/w 00000111 b9 h interrupt control register 09 icr09 r/w 00000111 ba h interrupt control register 10 icr10 r/w 00000111 bb h interrupt control register 11 icr11 r/w 00000111 bc h interrupt control register 12 icr12 r/w 00000111 bd h interrupt control register 13 icr13 r/w 00000111 be h interrupt control register 14 icr14 r/w 00000111 bf h interrupt control register 15 icr15 r/w 00000111 co to ff h external area 100 h to # h ram area # h to 1fef h reserved area table a.1a i/o map (continued) address register abbreviation access resource initial value a.1 i/o map MB90580 series appendix a: i/o map 307 1ff0 h program address detection register 0 padr0 r/w program patch manipulation xxxxxxxx 1ff1 h program address detection register 1 r/w xxxxxxxx 1ff02 h program address detection register 2 r/w xxxxxxxx 1ff3 h program address detection register 3 padr1 r/w xxxxxxxx 1ff4 h program address detection register 4 r/w xxxxxxxx 1ff5 h program address detection register 5 r/w xxxxxxxx 1ff6 h to 1fff h reserved area table a.1a i/o map (continued) address register abbreviation access resource initial value appendix b: instructions b.1 addressing in the f 2 mc-16lx, the address format is determined by either the instructions effective address specification, or by the instruction code itself (implied addressing). b.1.1 effective address field the address formats specified in the effective address field are shown in table b.1.1a. table b.1.1a effective address field code notation address format default bank 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct starting from the left, ea corresponds to the byte, word and long-word types. none 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect dtb dtb adb spb 0c 0d 0e 0f @rw0+ @rw1+ @rw2+ @rw3+ register indirect with post-incrementing dtb dtb adb spb 10 11 12 13 @rw0+disp8 @rw1+disp8 @rw2+disp8 @rw3+disp8 register indirect with 8-bit displacement dtb dtb adb spb 14 15 16 17 @rw4+disp8 @rw5+disp8 @rw6+disp8 @rw7+disp8 register indirect with 8-bit displacement dtb dtb adb spb 18 19 1a 1b @rw0+disp16 @rw1+disp16 @rw2+disp16 @rw3+disp16 register indirect with 16-bit displacement dtb dtb adb spb 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address dtb dtb pcb dtb b.1 addressing 310 appendix b: instructions MB90580 series b.1.2 addressing details (1) immediate value (#imm) this format specifies the operand value directly. ?#imm4 ?#imm8 ?#imm16 ?#imm32 (2) compressed direct address (dir) in this format, the operand specifies the low-order 8 bits of the memory address. bits 8 to 15 of the address are specified by the dpr. bits 16 to 23 of the address are indicated by the dtb. (3) direct address (addr16) in this format, the operand specifies the low-order 16 bits of the memory address. bits 16 to 23 of the address are indicated by the dtb. (4) register direct this format specifies a direct register as the operand. general-purpose registers byte: r0, r1, r2, r3, r4, r5, r6, r7 word: rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 long word: rl0, rl1, rl2, rl3 dedicated registers accumulator: a, al pointer: sp bank: pcb, dtb, usb, ssb, adb page: dpr control: ps, ccr, rp, ilm note: regarding the sp, either the usp or the ssp is selected and used, depending on the value of the s bit in the ccr. in addition, in a branching instruction, the pc is implicitly specified, and is not described in the instruction operand. b.1 addressing MB90580 series appendix b: instructions 311 (5) register indirect (@rwj j = 0 to 3) this format accesses the memory address indicated by the contents of the general-purpose register rwj. when rw0/rw1 is used, bits 16 to 23 of the address are indicated by dtb; if rw3 is used, bits 16 to 23 of the address are indicated by spb, and if rw2 is used, bits 16 to 23 of the address are indicated by adb. (6) register indirect with post-incrementing (@rwj+ j = 0 to 3) this format accesses the memory address indicated by the contents of the general-purpose register rwj. after the operand operation, rwj is incremented by the data length of the operand (by 1 for a byte, 2 for a word, and 4 for a long-word). when rw0/rw1 is used, bits 16 to 23 of the address are indicated by dtb; if rw3 is used, bits 16 to 23 of the address are indicated by spb, and if rw2 is used, bits 16 to 23 of the address are indicated by adb. note that if the post-incremented result is the address of the register for which the increment specification was made, the value that is referenced subsequently is the incremented value. in addition, in such a case, if the instruction was a write instruction, the data written by the instruction is given priority, so the register that was to have been incremented contains the write data in the end. (7) register indirect with displacement (@rwi + disp8 i= 0 to 7/@rwj + disp16 j = 0 to 3) this format accesses the memory address indicated by the sum of the contents of the general-purpose register rwj and the displacement value. the displacement value can be one of two types, either a byte or a word, and is added as a signed value. when rw0, rw1, rw4, or rw5 is used, bits 16 to 23 of the address are indicated by dtb; if rw3 or rw7 is used, bits 16 to 23 of the address are indicated by spb, and if rw2 or rw6 is used, bits 16 to 23 of the address are indicated by adb. (8) register indirect with base index (@rw0 + rw7, @rw1 + rw7) this format accesses the memory address indicated by the sum of the contents of the general-purpose register and either rw0 or rw1. bits 16 to 23 of the address are indicated by dtb. (9) program counter indirect with displacement (@pc + disp16) this format accesses the memory address indicated by the sum of the instruction address + 4 + disp16. the displacement value is a word length value. bits 16 to 23 of the address are indicated by pcb. the operand address is generally regarded as the next instruction address + disp16, but note that this does not hold true for the instructions indicated below: ? dbnz eam, rel ? dwbnz eam, rel ? mov eam, #imm8 ? movw eam, #imm16 ? cbne eam, #imm8, rel ? cwbne eam, #imm16, rel b.1 addressing 312 appendix b: instructions MB90580 series (10) accumulator indirect (@a) this format has two types: one in which the contents of al specify bits 00 to 15 of the address and dtb indicates bits 16 to 23; and one in which the low-order 24 bits of a specify bits 00 to 23 of the address. (11) i/o direct (io) in this format, the memory address of the operand is specified directly by the 8-bit displacement value. regardless of the value of dtb and dpr, the i/o space from 000000 h to 0000ff h is accessed. the access space specification prefix has no effect on this addressing format. (12) long register indirect with displacement (@rli + disp8 i = 0 to 3) this format accesses the memory address indicated by the low-order 24 bits of the sum of the contents of the general-purpose register rli plus the displacement value. the displacement value is 8 bits, and is added as a signed numeral. (13) compressed direct bit address (dir:bp) this format specifies the low-order 8 bits of the memory address with the operand. in addition, bits 8 to 15 of the address are indicated by dpr. finally, bits 16 to 23 of the address are indicated by dtb. the bit position is indicated by :bp, with larger numbers being closer to the msb and smaller numbers being closer to the lsb. (14) i/o direct bit address (io:bp) this format directly specifies a bit within a physical address from 000000 h to 0000ff h . the bit position is indicated by :bp, with larger numbers being closer to the msb and smaller numbers being closer to the lsb. (15) direct bit address (addr16:bp) this format directly specifies any bit within a 64-kilobyte region. bits 16 to 23 of the address are indicated by dtb. the bit position is indicated by :bp, with larger numbers being closer to the msb and smaller numbers being closer to the lsb. (16) register list (rlst) this format specifies the register that is the target of a stack push/pop instruction. fig. b.1.2a register list configuration a register is selected when the corresponding bit is 1, and is not selected when the corresponding bit is 0. rw7rw6rw5rw4rw3rw2rw1rw0 msb lsb b.1 addressing MB90580 series appendix b: instructions 313 (17) program counter relative branching address (rel) with this format, the address of the destination of a branching instruction is the sum of the value of the pc and the 8-bit displacement value. if the result exceeds 16 bits, the amount of the overflow is ignored and the bank register is not incremented or decremented; therefore, the address is kept within a 64-kilobyte bank. this format is used in unconditional and conditional branching instructions. bits 16 to 23 of the address are indicated by pcb. (18) direct branching address (addr16) with this format, the address of the destination of a branching instruction is specified directly by the displacement value. the displacement value is 16 bits, and indicates the branching destination within a logical memory space. this format is used in unconditional branching instructions and subroutine call instructions. bits 16 to 23 of the address are indicated by pcb. (19) physical direct branching address (addr24) with this format, the address of the destination of a branching instruction is specified directly by the displacement value. the displacement value is 24 bits, and specifies the physical address of the branching destination. this format is used in unconditional branching instructions, subroutine call instructions, and software interrupt instructions. (20) accumulator indirect branching address (@a) in this format, the 16 bits of the accumulator al specify the branching destination address. this address indicates a branching destination within a bank space; in this case, bits 16 to 23 of the address are indicated by the pcb. in the case of jctx, however, bits 16 to 23 of the address are indicated by dtb. this format is used in unconditional branching instructions. (21) vector address (#vct) the contents of the specified vector become the branching destination address. there are two data lengths for vector numbers: 4 bits and 8 bits. this format is used in subroutine call instructions and software interrupt instructions. (22) indirect specification branching address (@ear) the word data in the address indicated by ear is the branching destination address. (23) indirect specification branching address (@eam) the word data in the address indicated by eam is the branching destination address. b.2 instruction set 314 appendix b: instructions MB90580 series b.2 instruction set table b.2a explanation of items in table of instructions item explanation mnemonic upper-case letters and symbols: ....... described as they appear in assembler. lower-case letters: ............................. replaced when described in assembler. numbers after lower-case letters: ...... indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. see table 4.2.4 for details about meanings of letters in items. rg indicates the register access count during execution of instruction. used to calculate compensation values for cpu intermittent operation. b indicates the compensation value for calculating the number of actual cycles during execution of instruction. the number of actual cycles during execution of instruction is the compensation value summed with the value in the ~ column. operation indicates operation of instruction. lh indicates special operations involving bits 15 through 08 of the accumulator. z:........ transfers 0. x:........ sign-extended transfer through sign extension. -:......... transfers nothing. ah indicates special operations involving the high-order 16 bits in the accumulator. *:......... transfers from al to ah. -:......... no transfer. z:........ transfers 00 to ah. x:........ transfers 00 h or ff h to ah using sign extension al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). *:......... changes due to execution of instruction. -:......... no change. s:........ set by execution of instruction. r: ....... reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *:......... instruction is a read-modify-write instruction. -:......... instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. b.2 instruction set MB90580 series appendix b: instructions 315 ? number of execution cycles the number of cycles required for the execution of an instruction is obtained by summing the value shown in the table for the number of cycles for the instruction in question, the compensation value (which depends on certain conditions), and the number of cycles needed for the program fetch. when fetching a program in memory connected to the 16-bit bus, such as on-chip rom, a program fetch is performed for each two-byte (word) boundary crossed by the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases. when fetching a program in memory connected to the 8-bit external data bus, a program fetch is performed for each byte of the instruction being executed; therefore, if there is any interference with data access, etc., the number of execution cycles increases. in cpu intermittent operation, each access to general-purpose registers, internal rom, internal ram, internal i/o functions or external bus causes the cpu clock to pause for a fixed number of cycles determined by the cg1/cg0 bits in the low power consumption mode control register. for this reason, the number of machine clock cycles required to execute an instruction under cpu intermittent opera- tion is the normal number of cycles plus an offset number of cycles that is derived by multiplying the number of access operations by the length (in cycles) of the fixed pause. b.2 instruction set 316 appendix b: instructions MB90580 series table b.2b explanation of symbols in table of instructions symbol explanation a 32-bit accumulator the bit length varies according to the instruction. byte:............ low-order 8 bits of al word: .......... 16 bits of al long: ........... 32 bits of al:ah ah al high-order 16 bits of a low-order 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 compact direct addressing direct addressing physical direct addressing bits 0 to 15 of addr24 bits 16 to 23 of addr24 io i/o area (000000 h to 0000ff h ) #imm4 #imm8 #imm16 #imm32 ext(imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel ear eam branch specification relative to pc effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list b.2 instruction set MB90580 series appendix b: instructions 317 table b.2c effective address fields note: the number of bytes for address extension is indicated by the + symbol in the # (number of bytes) column in the table of instructions and by the number of bytes in the detailed instruction rules. code notation address format number of bytes in address extension [note] 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long- word types, starting from the left C 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0+ @rw1+ @rw2+ @rw3+ register indirect with post-incrementing 0 10 11 12 13 14 15 16 17 @rw0+disp8 @rw1+disp8 @rw2+disp8 @rw3+disp8 @rw4+disp8 @rw5+disp8 @rw6+disp8 @rw7+disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0+disp16 @rw1+disp16 @rw2+disp16 @rw3+disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2 b.2 instruction set 318 appendix b: instructions MB90580 series table b.2d number of execution cycles for each form of addressing note: (a) is used in the ~ (number of cycles) column, column b (compensation value) and in the detailed instruction rules in the table of instructions. table b.2e compensation values for number of cycles used to calculate number of actual cycles note: (b), (c), and (d) are used in the ~ (number of cycles) column, column b (compensation value) and in the detailed instruction rules in the table of instructions. when the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready. code operand (a) number of accesses for each form of addressing number of execution cycles for each form of addressing 00 to 07 ri rwi rli listed in table of instructions listed in table of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj+ 4 2 10 to 17 @rwi+disp8 2 1 18 to 1b @rwj+disp16 2 1 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long cycles access cycles cycles access cycles cycles access cycles internal register +0 1 +0 1 +0 2 internal ram even address internal ram odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +1 1 +4 2 +8 4 b.2 instruction set MB90580 series appendix b: instructions 319 table b.2f compensation values for number of cycles used to calculate number of program fetch cycles note: when the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these compensation values should be used for worst case calculations. instruction byte boundary word boundary internal memory C +2 external data bus (16 bits) C +3 external data bus (8 bits) +3 C b.2 instruction set 320 appendix b: instructions MB90580 series b.2.1 f 2 mc-16lx instruction set (351 instructions) table b.2.1a transfer instructions (byte) (41 instructions) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a,dir mov a,addr16 mov a,ri mov a,ear mov a,eam mov a,io mov a,#imm8 mov a,@a mov a,@rli+disp8 movn a,#imm4 movx a,dir movx a,addr16 movx a,ri movx a,ear movx a,eam movx a,io movx a,#imm8 movx a,@a movx a,@rwi+disp8 movx a,@rli+disp8 mov dir,a mov addr16,a mov ri,a mov ear,a mov eam,a mov io,a mov @rli+disp8,a mov ri,ear mov ri,eam mov ear,ri mov eam,ri mov ri,#imm8 mov io,#imm8 mov dir,#imm8 mov ear,#imm8 mov eam,#imm8 mov @al,ah / mov @a,t xch a,ear xch a,eam xch ri,ear xch ri,eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+(a) 3 2 3 10 1 3 4 2 2 3+(a) 3 2 3 5 10 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 4 5+(a) 7 9+(a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2(b) 0 2(b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? (imm8) byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? (imm8) byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli)+disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ?? (ear) byte (a) ?? (eam) byte (ri) ?? (ear) byte (ri) ?? (eam) z z z z z z z z z z x x x x x x x x x x - - - - - - - - - - - - - - - - - z z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b.2 instruction set MB90580 series appendix b: instructions 321 table b.2.1b transfer instructions (word/long-word) (38 instructions) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movw a,dir movw a,addr16 movw a,sp movw a,rwi movw a,ear movw a,eam movw a,io movw a,@a movw a,#imm16 movw a,@rwi+disp8 movw a,@rli+disp8 movw dir,a movw addr16,a movw sp,a movw rwi,a movw ear,a movw eam,a movw io,a movw @rwi+disp8,a movw @rli+disp8,a movw rwi,ear movw rwi,eam movw ear,rwi movw eam,rwi movw rwi,#imm16 movw io,#imm16 movw ear,#imm16 movw eam,#imm16 movw @al,ah / movw @a,t xchw a,ear xchw a,eam xchw rwi,ear xchw rwi,eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+(a) 3 3 2 5 10 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 4 5+(a) 7 9+(a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2(c) 0 2(c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi)+disp8) word (a) ? ((rli)+disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi)+disp8) ? (a) word ((rli)+disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ?? (ear) word (a) ?? (eam) word (rwi) ?? (ear) word (rwi) ?? (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - movl a,ear movl a,eam movl a,#imm32 movl ear,a movl eam,a 2 2+ 5 2 2+ 4 5+(a) 3 4 5+(a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear1) ? (a) long (eam1) ? (a) - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * - - - - - - - - - - - - - - - b.2 instruction set 322 appendix b: instructions MB90580 series table b.2.1c addition and subtraction instructions (byte/word/long-word) (42 instructions) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw add a,#imm8 add a,dir add a,ear add a,eam add ear,a add eam,a addc a addc a,ear addc a,eam adddc a sub a,#imm8 sub a,dir sub a,ear sub a,eam sub ear,a sub eam,a subc a subc a,ear subc a,eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2(b) 0 0 (b) 0 0 (b) 0 (b) 0 2(b) 0 0 (b) 0 byte (a) ? (a) + imm8 byte (a) ? (a) + (dir) byte (a) ? (a) + (ear) byte (a) ? (a) + (eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (hexadecimal) byte (a) ? (a) - imm8 byte (a) ? (a) - (dir) byte (a) ? (a) - (ear) byte (a) ? (a) - (eam) byte (ear) ? (ear) - (a) byte (eam) ? (eam) - (a) byte (a) ? (ah) - (al) - (c) byte (a) ? (a) - (ear) - (c) byte (a) ? (a) - (eam) - (c) byte (a) ? (ah) - (al) - (c) (hexadecimal) z z z z - z z z z z z z z z - - z z z z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - addw a addw a,ear addw a,eam addw a,#imm16 addw ear,a addw eam,a addcw a,ear addcw a,eam subw a subw a,ear subw a,eam subw a,#imm16 subw ear,a subw eam,a subcw a,ear subcw a,eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2(c) 0 (c) 0 0 (c) 0 0 2(c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) - (al) word (a) ? (a) - (ear) word (a) ? (a) - (eam) word (a) ? (a) - imm16 word (ear) ? (ear) - (a) word (eam) ? (eam) - (a) word (a) ? (a) - (ear) - (c) word (a) ? (a) - (eam) - (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - * - - addl a,ear addl a,eam addl a,#imm32 subl a,ear subl a,eam subl a,#imm32 2 2+ 5 2 2+ 5 6 7+(a) 4 6 7+(a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) - (ear) long (a) ? (a) - (eam) long (a) ? (a) - imm32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - b.2 instruction set MB90580 series appendix b: instructions 323 table b.2.1d increment and decrement instructions (byte/word/long-word) (12 instructions) table b.2.1e compare instructions (byte/word/long-word) (11 instructions) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 3 5+(a) 3 5+(a) 2 0 2 0 0 2(b) 0 2(b) byte (ear) ? (ear) + 1 byte (eam) ? (eam) + 1 byte (ear) ? (ear) - 1 byte (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+(a) 3 5+(a) 2 0 2 0 0 2(c) 0 2(c) word (ear) ? (ear) + 1 word (eam) ? (eam) + 1 word (ear) ? (ear) - 1 word (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+(a) 7 9+(a) 4 0 4 0 0 2(d) 0 2(d) long (ear) ? (ear) + 1 long (eam) ? (eam) + 1 long (ear) ? (ear) - 1 long (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a,ear cmp a,eam cmp a,#imm8 1 2 2+ 2 1 2 3+(a) 2 0 1 0 0 0 0 (b) 0 byte (ah) - (al) byte (a) - (ear) byte (a) - (eam) byte (a) - imm8 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - cmpw a cmpw a,ear cmpw a,eam cmpw a,#imm16 1 2 2+ 3 1 2 3+(a) 2 0 1 0 0 0 0 (c) 0 word (ah) - (al) word (a) - (ear) word (a) - (eam) word (a) - imm16 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - cmpl a,ear cmpl a,eam cmpl a,#imm32 2 2+ 5 6 7+(a) 3 2 0 0 0 (d) 0 long (a) - (ear) long (a) - (eam) long (a) - imm32 - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - b.2 instruction set 324 appendix b: instructions MB90580 series table b.2.1f unsigned multiplication and division instructions (word/long-word) (11 instructions) *1: 3 when dividing into zero, 7 when an overflow occurs, and 15 normally. *2: 4 when dividing into zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when dividing into zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when dividing into zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when dividing into zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not 0. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not 0. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not 0. *12: 4 when word (ear) is zero, and 12 when word (ear) is not 0. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not 0. note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a,ear divu a,eam divuw a,ear divuw a,eam mulu a mulu a,ear mulu a,eam muluw a muluw a,ear muluw a,eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 1 0 1 0 0 1 0 0 1 0 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) / byte (al) quotient ? byte (al) remainder ? byte (ah) word (a) / byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a) / byte (eam) quotient ? byte (a) remainder ? byte (ear) long (a) / word (ear) quotient ? word (a) remainder ? word (ear) long (a) / word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) * byte (al) ? word (a) byte (a) * byte (ear) ? word (a) byte (a) * byte (eam) ? word (a) word (ah) * word (al) ? long (a) word (a) * word (ear) ? long (a) word (a) * word (eam) ? long (a) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - b.2 instruction set MB90580 series appendix b: instructions 325 table b.2.1g signed multiplication and division instructions (word/long-word) (11 instructions) *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: when dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. when dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: when dividend is positive: 4+ (a) when dividing into zero, 11+ (a) or 30+ (a) when an overflow occurs, and 31+ (a) normally. when dividend is negative: 4+ (a) when dividing into zero, 12+ (a) or 31+ (a) when an overflow occurs, and 32+ (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, 12 when the result is possible, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is possible, and 13 when the result is negative. *10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: 3 when word (ah) is zero, 12 when the result is possible, and 13 when the result is negative. *12: 3 when word (ear) is zero, 16 when the result is possible, and 19 when the result is negative. *13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: two cycle counts are given for overflows occurring from div or divw instructions, because the overflow may be detected before or after execution. the contents of al are destroyed when an overflow occurs from a div or divw instruction. for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw div a div a,ear div a,eam divw a,ear divw a,eam mul a mul a,ear mul a,eam mulw a mulw a,ear mulw a,eam 1 2 2+ 2 2+ 2 2 2+ 2 2 2+ *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 1 0 1 0 0 1 0 0 1 0 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) / byte (al) quotient ? byte (al) remainder ? byte (ah) word (a) / byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a) / byte (eam) quotient ? byte (a) remainder ? byte (ear) long (a) / word (ear) quotient ? word (a) remainder ? word (ear) long (a) / word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) * byte (al) ? word (a) byte (a) * byte (ear) ? word (a) byte (a) * byte (eam) ? word (a) word (ah) * word (al) ? long (a) word (a) * word (ear) ? long (a) word (a) * word (eam) ? long (a) z z z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - - b.2 instruction set 326 appendix b: instructions MB90580 series table b.2.1h logical 1 instructions (byte/word) (39 instructions) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a,#imm8 and a,ear and a,eam and ear,a and eam,a or a,#imm8 or a,ear or a,eam or ear,a or eam,a xor a,#imm8 xor a,ear xor a,eam xor ear,a xor eam,a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2(b) 0 0 (b) 0 2(b) 0 0 (b) 0 2(b) 0 0 2(b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * andw a andw a,#imm16 andw a,ear andw a,eam andw ear,a andw eam,a orw a orw a,#imm16 orw a,ear orw a,eam orw ear,a orw eam,a xorw a xorw a,#imm16 xorw a,ear xorw a,eam xorw ear,a xorw eam,a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2(c) 0 0 0 (c) 0 2(c) 0 0 0 (c) 0 2(c) 0 0 2(c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - - * - - - - - * - - * b.2 instruction set MB90580 series appendix b: instructions 327 table b.2.1i logical 2 instructions (long-word) (6 instructions) table b.2.1j sign inversion instructions (byte/word) (6 instructions) table b.2.1k normalize instruction (long-word) (1 instruction) *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases. note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw andl a,ear andl a,eam orl a,ear orl a,eam xorl a,ear xorl a,eam 2 2+ 2 2+ 2 2+ 6 7+(a) 6 7+(a) 6 7+(a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * r r r r r r - - - - - - - - - - - - mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+(a) 0 2 0 0 0 2+(b) byte (a) ? 0 - (a) byte (ear) ? 0 - (ear) byte (eam) ? 0 - (eam) x - - - - - - - - - - - - - - * * * * * * * * * * * * - - * negw a negw ear negw eam 1 2 2+ 2 2 5+(a) 0 2 0 0 0 2+(c) word (a) ? 0 - (a) word (ear) ? 0 - (ear) word (eam) ? 0 - (eam) - - - - - - - - - - - - - - - * * * * * * * * * * * * - - * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a,r0 2 *1 1 0 long (a) ? shift to the position where 1 was formerly placed byte (r0) ? number of shifts at that time ------ * -- - b.2 instruction set 328 appendix b: instructions MB90580 series table b.2.1l shift instructions (byte/word/long-word) (18 instructions) *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a,ro lsr a,ro lsl a,ro 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+(a) 3 5+(a) *1 *1 *1 0 0 2 0 2 0 1 1 1 0 0 0 2(b) 0 2(b) 0 0 0 byte (a) ? right rotate with carry byte (a) ? left rotate with carry byte (ear) ? right rotate with carry byte (eam) ? right rotate with carry byte (ear) ? left rotate with carry byte (eam) ? left rotate with carry byte (a) ? arithmetic right barrel shift (a,r0) byte (a) ? logical right barrel shift (a,r0) byte (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * - - - * - * - - - asrw a lsrw a /shrw a lslw a /shlw a asrw a,r0 lsrw a,r0 lslw a,r0 1 1 1 2 2 2 2 2 2 *1 *1 *1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a,1 bit) word (a) ? logical right shift (a,1 bit) word (a) ? logical left shift (a,1 bit) word (a) ? arithmetic right barrel shift (a,r0) word (a) ? logical right barrel shift (a,r0) word (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * r * * * * * * * * * * - - - - - - * * * * * * - - - - - - asrl a,r0 lsrl a,r0 lsll a,r0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (a) ? arithmetic right barrel shift (a,r0) long (a) ? logical right barrel shift (a,r0) long (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - * * - * * * * * * - - - * * * - - - b.2 instruction set MB90580 series appendix b: instructions 329 table b.2.1m branch 1 instructions (31 instructions) *1: 4 when branching, 3 when not branching. *2: 3 (c) + (b) note 1: read (word) branch address. note 2: w: save (word) into stack; r: read (word) branch address. note 3: save (word) into stack. note 4: w: save (long-word) into w stack; r: read (long-word) r branch address. note 5: save (long-word) into stack. note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw bz / beq rel bnz / bne rel bc / blo rel bnc / bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear *1 jmpp @eam *1 jmpp addr24 call @ear *2 call @eam *2 call addr16 *3 callv #vct4 *3 callp @ear *4 callp @eam *4 callp addr24 *5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+(a) 5 6+(a) 4 6 7+(a) 6 7 10 11+(a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2(c) (c) 2(c) 2(c) *2 2(c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 unconditional branching word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear+2) word (pc) ? (eam), (pcb) ? (eam+2) word (pc) ? ad24 0-15, (pcb) ? ad24 16-23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0-15, (pcb) ? (ear)16-23 word (pc) ? (eam) 0-15, (pcb) ? (eam)16-23 word (pc) ? addr0-15, (pcb) ? addr16-23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b.2 instruction set 330 appendix b: instructions MB90580 series table b.2.1n branch 2 instructions (19 instructions) *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: 3 (b) + 2 (c) when an interrupt request is generated, 6 (c) at recovery. note 1: return from stack (word) note 2: return from stack (long) note 3: rwj+ addressing mode should not be used with the cbne/cwbne instructions. note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw cbne a,#imm8,rel cwbne a,#imm16,rel cbne ear,#imm8,rel cbne eam,#imm8,rel cwbne ear,#imm16,rel cwbne eam,#imm16,rel dbnz ear,rel dbnz eam,rel dwbnz ear,rel dwbnz eam,rel int #vct8 int addr16 intp addr24 int9 reti link #imm8 unlink ret *1 retp *2 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 *1 *1 *2 *3 *4 *3 *5 *6 *5 *6 20 16 17 20 11 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2(b) 0 2(c) 8(c) 6(c) 6(c) 8(c) *7 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear)=(ear)-1, (ear) 1 0 branch when byte (eam)=(eam)-1, (eam) 1 0 branch when word (ear)=(ear)-1, (ear) 1 0 branch when word (eam)=(eam)-1, (eam) 1 0 software interrupt software interrupt software interrupt software interrupt recovery from interrupt at the entrance of function, save old frame pointers into a stack, set up new frame point- ers, reserve area for local pointers. at the exit of function, recover the old frame pointers from the stack. recover from the subroutine. recover from the subroutine. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - r r r r * - - - - - - - - - - - - - - s s s s * - - - - - - - - - - - - - - - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * - - - - - - - - * - - - - - - - - - - - * - * - - - - - - - - - b.2 instruction set MB90580 series appendix b: instructions 331 table b.2.1o other control instructions (byte/word/long-word) (36 instructions) *1: pcb, adb, ssb, usb, and spb: ...1 cycle dtb, dpr: ......................................2 cycles *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 *3: 29 + 3 (pop count) - 3 (last register number to be popped), 8 when rlst = 0 *4: pop count x (c), or push count x (c) note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr,#imm8 or ccr,#imm8 mov rp,#imm8 mov ilm,#imm8 movea rwi,ear movea rwi,eam movea a,ear movea a,eam addsp #imm8 addsp #imm16 mov a,brgl mov brg2,a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+(a) 1 1+(a) 3 3 *1 1 1 1 1 1 1 1 1 0 0 0 +& 0 0 0 +& 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) *4 (c) (c) (c) *4 6(c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) -2, ((sp)) ? (a) word (sp) ? (sp) -2, ((sp)) ? (ah) word (sp) ? (sp) -2, ((sp)) ? (ps) (sp) ? (sp) - 2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? (sp) + 2 word (ah) ? ((sp)), (sp) ? (sp) + 2 word (ps) ? ((sp)), (sp) ? (sp) + 2 (rlst) ? ((sp)), (sp) ? (sp) context switching instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word (a) ? ear word (a) ? eam word (sp) ? ext(imm8) word (sp) ? imm16 byte (a) ? (brg1) byte (brg2) ? (a) no operation prefix code for ad space access prefix code for dt space access prefix code for pc space access prefix code for sp space access prefix code for flag unchange setting prefix for common register banks - - - - - - - - - - - - - - - - - - - z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - b.2 instruction set 332 appendix b: instructions MB90580 series table b.2.1p bit manipulation instructions (22 instructions) *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a,dir:bp movb a,addr16:bp movb a,io:bp movb dir:bp,a movb addr16:bp,a movb io:bp,a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp,rel bbc addr16:bp,rel bbc io:bp,rel bbs dir:bp,rel bbs addr16:bp,rel bbs io:bp,rel sbbs addr16:bp,rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) (b) (b) (b) (b) (b) (b) 2(b) *5 *5 byte (a) ? ( dir:bp )b byte (a) ? ( addr16:bp )b byte (a) ? ( io:bp )b bit ( dir:bp )b ? (a) bit ( addr16:bp )b ? (a) bit ( io:bp )b ? (a) bit ( dir:bp )b ? 1 bit ( addr16:bp )b ? 1 bit ( io:bp )b ? 1 bit ( dir:bp )b ? 0 bit ( addr16:bp )b ? 0 bit ( io:bp )b ? 0 branch when ( dir:bp )b = 0 branch when ( addr16:bp )b = 0 branch when ( io:bp)b = 0 branch when ( dir:bp )b = 1 branch when ( addr16:bp )b = 1 branch when ( io:bp)b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - b.2 instruction set MB90580 series appendix b: instructions 333 table b.2.1q accumulator manipulation instructions (byte/word) (6 instructions) table b.2.1r string instructions (10 instructions) *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7n + 5 when match occurs. *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case. *3: (b) (rw0) + (b) (rw0): when accessing a source and a destination in different areas, the value of item (b) should be computed separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0): when accessing a source and a destination in different areas, the value of item (c) should be computed separately for each. *7: (c) n *8: 2 (rw0) m : rw0 value (counter value) n : loop count note: for an explanation of (a) to (d) in the colunm b, see table b.2d and table b.2e. mnemonic # ~ rg b operation lh ah i s t n z v c rmw swap swapw / xchw a,t ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a)0-7 ?? (a)8-15 word (ah) ?? (al) byte signed extension word signed extension byte zero extension word zero extension - - x - z - - * - x - z - - - - - - - - - - - - - - - - - - - - * * r r - - * * * * - - - - - - - - - - - - - - - - - - mnemonic # ~ rg b operation lh ah i s t n z v c rmw movs / movsi movsd sceq / sceqi sceqd fils / filsi 2 2 2 2 2 *2 *2 *1 *1 6m+6 +& +& +& +& +& *3 *3 *4 *4 *3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ah- ? @al-, counter = rw0 byte search @ah+ ? al, counter = rw0 byte search @ah- ? al, counter = rw0 byte fill @ah+ ? al, counter = rw0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * - - - * * - - - - - - movsw / movswi movswd scweq / scweqi scweqd filsw / filswi 2 2 2 2 2 *2 *2 *1 *1 6m+6 +) +) +) +) +) *6 *6 *7 *7 *6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ah- ? @al-, counter = rw0 word search @ah+ ? al, counter = rw0 word search @ah- ? al, counter = rw0 word fill @ah+ ? al, counter = rw0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * - - - * * - - - - - - b.3 instruction map 334 appendix b: instructions MB90580 series b.3 instruction map because the f 2 mc-16lx operation codes each consist of one or two bytes, the instruction map consists of numerous pages. the structure of the instruction map is shown below. fig. b.3a structure of f 2 mc-16lx instruction map instructions that consist of only one byte (such as nop) are concluded on the basic page. regarding instructions that require two bytes (such as movs), the existence of the map for the second byte is indicated when the first byte is referenced, so it is clear that it is necessary to use the following byte to reference the map for the second byte. basic page map first byte 2-byte instructions bit manipulation ea instructions 9 second byte instructions character string manipulation instructions b.3 instruction map MB90580 series appendix b: instructions 335 the correspondence between the actual instruction code and the instruction map is shown below. fig. b.3b correspondence between actual instructions and the instruction maps instruction code first byte second byte operand operand may not exist for some instructions length differs according to the [basic page map] [extension page map] note ? ? ? xy uv +w +z ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? instruction note: extended page maps are provided for bit manipulation instructions, character string manipulation instructions, two-byte instructions, and ea instructions; multiple-extended-page maps exist for each type of instruction. b.3 instruction map 336 appendix b: instructions MB90580 series b.3.1 basic page map table b.3.1a basic page map 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + a + b + c + d + e + f nop int9 adddc neg pcb dtb adb spb link unlink mov negw lslw asrw lsrw imm#8 cmr ncc subdc jctx ext zext swap addsp addl subl mov cmpl extw zextw swapw addsp a ilm, #8 #16 add sub addc cmp and or divu mulu addw subw cbne a, cmpw andw orw xorw muluw a, dir a, dir a a ccr, #8 ccr, #8 a a a a #8, rel a a a a a add sub subc cmp and or xor not addw subw cwbne cmpw andw orw xorw notw a, #8 a, #8 a a, #8 a, #8 a, #8 a, #8 a a, #16 a, #16 a, #16, rel a, #16 a, #16 a, #16 a, #16 a mov a, dir mov dir, a mov a, #8 movx a, #8 mov dir, #8 movx a, dir movw a, sp movw sp, a movw a, dir movw dir, a movw a, #16 movl a, #32 pushw a pushw ah pushw ps pushw rlst mov a, io mov io, a mov a, addr16 mov addr 16, a mov io, #8 movx a, io movw io, #16 movx a, addr16 movw a, io movw io, a movw a, addr16 movw addr16, a popw a popw ah popw ps popw rlst bra rel jmp @a jmp addr16 jmpp addr24 call addr16 callp addr24 retp ret int #vct8 int addr16 intp addr24 reti bit string two-byte operation instructions instructions operation instructions ea instructions (1) ea ea ea ea ea ea ea ea movea rwi, ea mov ri, ea movw rwi, ea mov ea, ri movw ea, rwi xch ri, ea xcrw rwi, ea instructions (2) instructions (3) instructions (4) instructions (5) instructions (6) instructions (7) instructions (8) instructions (9) mov a, ri mov ri, a mov ri, #8 movx a, ri movx a,@rwi+d8 movn a, #4 callv #4 bz /beq rel bnz/bne rel bc /blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel movw a, rwi movw rwi, a movw rwi, #16 movw @rwi+db movw @rwi+db, a a a rp, #8 a @a #8 a, #32 a, #32 a a a a, #32 b.3 instruction map MB90580 series appendix b: instructions 337 table b.3.1b bit manipulation instruction map (first byte = 6 c h ) 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0 e 0f 0 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + a + b +c +d + e + f movb a, io:bp movb io:bp, a clrb io:bp setb io:bp bbs io:bp, rel bbc io:bp, rel wbts io:bp wbtc io:bp movb a, dir:bp movb a, addr16:bp movb dir: bp,a movb addr16: bp, a clrb dir:bp clrb addr16:bp setb dir:bp setb addr16:bp bbc dir:bp,rel bbc ad16:bp, rel bbs ad 16:bp, rel bbs dir:bp, rel sbbs addr16:bp b.3 instruction map 338 appendix b: instructions MB90580 series table b.3.1c character string manipulation instruction map (first byte = 6e h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 movsi movsd movswi movswd pcb, pcb pcb, dtb pcb, adb pcb, spb dtb, pcb dtb, dtb dtb, adb dtb, spb adb, pcb adb, dtb adb, adb adb, spb spb, pcb spb, dtb spb, adb spb, spb sceqi sceqd scweqi scweqd filsi filswi pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb b.3 instruction map MB90580 series appendix b: instructions 339 table b.3.1d two-byte instruction map (first byte = 6f h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 mov a, dtb mov a, adb mov a, ssb mov a, usb mov a. dpr mov a. @a mov a, pcb rolc a lslw a, r0 movw a, @a asrw a, r0 lsrw a, r0 mov dtb, a mov adb, a mov ssb, a mov usb, a mov dpr, a mov @al, ah movx a, @a rorc a lsll a, r0 movw @al, ah asrl a, r0 lsrl a, r0 movx a, @rl0 +d8 movx a, @rl1+d8 movx a, @rl2+d8 movx a, @rl3+d8 lsl a, r0 nrml a, r0 asr a, r0 lsr a, r0 mov @rl0+d8, a mov @rl1+d8, a mov @rl2+d8, a mov @rl3+d8, a mov a, @rl0+d8 mov a, @rl1+d8 mov a, @rl2+d8 mov a, @rl3+d8 movw @rl0+d8, a movw @rl1+d8, a movw @rl2+d8, a movw @rl3+d8, a movw a, @rl0+d8 movw a, @rl1+d8 movw a, @rl2+d8 movw a, @rl3+d8 mul a mulw a divu a b.3 instruction map 340 appendix b: instructions MB90580 series table b.3.1e ea instructions 1 (first byte = 70 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 addl a, rl0 addl a, rl0 addl a, rl1 addl a, rl1 addl a, rl2 addl a, rl2 addl a, rl3 addl a, rl3 addl a, @rw0 addl a, @rw1 addl a, @rw2 addl a, @rw3 addl a, @rw0+ addl a, @rw1+ addl a, @rw2+ addl a, @rw3+ addl a, @rw0+d8 addl a, @rw1+d8 addl a, @rw2+d8 addl a, @rw3+d8 addl a, @rw4+d8 addl a, @rw5+d8 addl a, @rw6+d8 addl a, @rw7+d8 addl a, @rw0+d16 addl a, @rw1+d16 addl a, @rw2+d16 addl a, @rw3+d16 addl a, @rw0+rw7 addl a, @rw1+rw7 addl a, @pc+d16 addl a, addr16 andl a, rl0 andl a, rl0 andl a, rl1 andl a, rl1 andl a, rl2 andl a, rl2 andl a, rl3 andl a, rl3 andl a, @rw0 andl a, @rw1 andl a, @rw2 andl a, @rw3 andl a, @rw0+ andl a, @rw1+ andl a, @rw2+ andl a, @rw3+ subl a, rl0 subl a, rl0 subl a, rl1 subl a, rl1 subl a, rl2 subl a, rl2 subl a,rl3 subl a, rl3 a, @rw0 subl a, @rw1 subl a, @rw2 subl a, @rw3 subl a, @rw0+ subl a, @rw1+ subl a, @rw2+ subl a, @rw3+ subl a, @rw0+d8 subl a, @rw1+d8 subl a, @rw2+d8 subl a, @rw3+d8 subl a, @rw4+d8 subl a, @rw5+d8 subl a, @rw6+d8 subl a, subl a, @rw0+d16 subl a, @rw1+d16 subl a, @rw2+d16 subl a, @rw3+d16 subl a, @rw0+rw7 subl a, @rw1+rw7 subl a, @pc+d16 subl a, addr16 cwbne rw0, #16, rel cwbne rw1, #16, rel cwbne rw2, #16, rel cwbne rw3, #16, rel cwbne rw4, #16, rel cwbne rw5, #16, rel cwbne rw6, #16, rel cwbne rw7, #16, rel cwbne @ rw0, #16, rel cwbne @ rw1, #16, rel cwbne @ rw2, #16, rel cwbne @ rw3, #16, rel cwbne @rw1+rw7 ,#16, rel cwbne @pc+d16, #16, rel cwbne addr16, #16, rel cwbne @rw0+d8, #16, rel cwbne @rw1+d8, #16, rel cwbne @rw2+d8, #16, rel cwbne @rw3+d8, #16, rel cwbne @rw4+d8, #16, rel cwbne @rw5+d8, #16, rel cwbne @rw6+d8, #16, rel cwbne @rw7+d8, #16, rel cwbne @rw0+d16, #16, rel cwbne @rw1, d16, #16, rel cwbne @rw2+d16, #16, rel cwbne @rw3+d16, #16, rel cwbne @rw0+rw7 ,#16, rel cmpl a, @rw0+d8 cmpl a, @rw1+d8 cmpl a, @rw2+d8 cmpl a, @rw3+d8 cmpl a, @rw4+d8 cmpl a, @rw5+d8 cmpl a, @rw6+d8 cmpl a, @rw7+d8 cmpl a, @rw0+d16 cmpl a, @rw1+d16 cmpl a, @rw2+d16 cmpl a, @rw3+d16 cmpl a, @rw0+rw7 cmpl a, @rw1+rw7 cmpl a, @pc+d16 cmpl a, addr16 cmpl a, rl0 cmpl a, rl0 cmpl a, rl1 cmpl a, rl1 cmpl a, rl2 cmpl a, rl2 cmpl a, rl3 cmpl a, rl3 cmpl a, @rw0 cmpl a, @rw1 cmpl a, @rw2 cmpl a, @rw3 cmpl a, @rw0+ cmpl a, @rw1+ cmpl a, @rw2+ cmpl a, @rw3+ andl a, @rw0+d8 andl a, @rw1+d8 andl a, @rw2+d8 andl a, @rw3+d8 andl a, @rw4+d8 andl a, @rw5+d8 andl a, @rw6+d8 andl a, @rw7+d8 andl a, @rw0+d16 andl a, @rw1+d16 andl a, @rw2+d16 andl a, @rw3+d16 andl a, @rw0+rw7 andl a, @rw1+rw7 andl a, @pc+d16 andl a, addr16 orl a, @rw0+d8 orl a, @rw1+d8 orl a, @rw2+d8 orl a, @rw3+d8 orl a, @rw4+d8 orl a, @rw5+d8 orl a, @rw6+d8 orl a, @rw7+d8 orl a, @rw0+d16 orl a, @rw1+d16 orl a, @rw2+d16 orl a, @rw3+d16 orl a, @rw0+rw7 orl a, @rw1+rw7 orl a, @pc+d16 orl a, addr16 xorl a, @rw0+d8 xorl a, @rw1+d8 xorl a, @rw2+d8 xorl a, @rw3+d8 xorl a, @rw4+d8 xorl a, @rw5+d8 xorl a, @rw6+d8 xorl a, @rw7+d8 xorl a, @rw0+d16 xorl a, @rw1+d16 xorl a, @rw2+d16 xorl a, @rw3+d16 xorl a, @rw0+rw7 xorl a, @rw1+rw7 xorl a, @pc+d16 xorl a, addr16 orl a, rl0 orl a, rl0 orl a, rl1 orl a, rl1 orl a, rl2 orl a, rl2 orl a, rl3 orl a, rl3 orl a, @rw0 orl a, @rw1 orl a, @rw2 orl a, @rw3 orl a, @rw0+ orl a, @rw1+ orl a, @rw2+ orl a, @rw3+ xorl a, rl0 xorl a, rl0 xorl a, rl1 xorl a, rl1 xorl a, rl2 xorl a, rl2 xorl a, rl3 xorl a, rl3 xorl a, @rw0 xorl a, @rw1 xorl a, @rw2 xorl a, @rw3 xorl a, @rw0+ xorl a, @rw1+ xorl a, @rw2+ xorl a, @rw3+ cbne r0, #8, rel cbne r1, #8, rel cbne r2, #8, rel cbne r3, #8, rel cbne r4, #8, rel cbne r5, #8, rel cbne r6, #8, rel cbne r7, #8, rel cbne @rw0, #8, rel cbne @rw1, #8, rel cbne @rw2, #8, rel cbne @rw3, #8, rel cbne @rw1+rw7 #8, rel cbne @pc+d16, #8, rel cbne addr16, #8, rel cbne @rw0+d8, #8, rel cbne @rw1+d8, #8, rel cbne @rw2+d8, #8, rel cbne @rw4+d8, #8, rel cbne @rw6+d8, #8, rel cbne @rw7+d8, #8, rel cbne @rw0+d16, #8, rel cbne @rw1+d16, #8, rel cbne @rw2+d16, #8, rel cbne @rw3+d16, #8, rel cbne @rw0+rw7 , #8, rel cbne @rw3+d8, #8, rel cbne @rw5+d8, #8, rel subl @rw7+d8 prohibit prohibit prohibit prohibit prohibit prohibit prohibit prohibit b.3 instruction map MB90580 series appendix b: instructions 341 table b.3.1f ea instructions 22 (first byte = 71 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 jmpp @rl0 jmpp @rl0 jmpp @rl1 jmpp @rl1 jmpp @rl2 jmpp @rl2 jmpp @rl3 jmpp @rl3 jmpp @@rw0 jmpp @@rw1 jmpp @@rw2 jmpp @@rw3 jmpp @@rw0+ jmpp @@rw1+ jmpp @@rw2+ jmpp @@rw3+ jmpp @@rw0+d8 jmpp @@rw1+d8 jmpp @@rw2+d8 jmpp @@rw3+d8 jmpp @@rw4+d8 jmpp @@rw5+d8 jmpp @@rw6+d8 jmpp @@rw7+d8 jmpp @ @rw0+d16 jmpp @ @rw1+d16 jmpp @ @rw2+d16 jmpp @ @rw3+d16 jmpp @ @rw0+rw7 jmpp @ @rw1+rw7 jmpp @@pc+d16 jmpp @addr16 callp @rl0 callp @rl0 callp @rl1 callp @rl1 callp @rl2 callp @rl2 callp @rl3 callp @rl3 callp @@rw0 callp @@rw1 callp @@rw2 callp @@rw3 callp @@rw0+ callp @@rw1+ callp @@rw2+ callp @@rw3+ incl rl0 incl rl0 incl rl1 incl rl1 incl rl2 incl rl2 incl rl3 incl rl3 incl @rw0 incl @rw1 incl @rw2 incl @rw3 incl @rw0+ incl @rw1+ incl @rw2+ incl @rw3+ decl rl0 decl rl0 decl rl1 decl rl1 decl rl2 decl rl2 decl rl3 decl rl3 decl @rw0 decl @rw1 decl @rw2 decl @rw3 decl @rw0+ decl @rw1+ decl @rw2+ decl @rw3+ movl a, rl0 movl a, rl0 movl a, rl1 movl a, rl1 movl a, rl2 movl a, rl2 movl a, rl3 movl a, rl3 movl a, @rw0 movl a, @rw1 movl a, @rw2 movl a,@ rw3 movl a, @rw0+ movl a, @rw1+ movl a, @rw2+ movl a, @rw3+ movl rl0, a movl rl0, a movl rl1, a movl rl1, a movl rl2, a movl rl2, a movl rl3, a movl rl3, a movl @rw0, a movl @rw1, a movl @rw2, a movl @rw3, a movl @rw0+, a movl @rw1+, a movl @rw2+, a movl @rw3+, a mov r0, #8 mov r1, #8 mov r2, #8 mov r3, #8 mov r4, #8 mov r5, #8 mov r6, #8 mov r7, #8 mov @rw0, #8 mov @rw1, #8 mov @rw2, #8 mov @rw3, #8 mov @rw0+, #8 mov @rw1+, #8 mov @rw2+, #8 mov @rw3+, #8 movea a, rw0 movea a, rw1 movea a, rw2 movea a, rw3 movea a, rw4 movea a, rw5 movea a, rw6 movea a, rw7 movea a, @rw0 movea a, @rw1 movea a, @rw2 movea a, @rw3 movea a, @rw0+ movea a, @rw1+ movea a, @rw2+ movea a, @rw3+ callp @@rw0+d8 callp @@rw1+d8 callp @@rw2+d8 callp @@rw3+d8 callp @@rw4+d8 callp @@rw5+d8 callp @@rw6+d8 callp @@rw7+d8 callp @ @rw0+d16 callp @ @rw1+d16 callp @ @rw2+d16 callp @ @rw3+d16 callp @ @rw0+rw7 callp @ @rw1+rw7 callp @@pc+d16 callp @addr16 incl @rw0+d8 incl @rw1+d8 incl @rw2+d8 incl @rw3+d8 incl @rw4+d8 incl @rw5+d8 incl @rw6+d8 incl @rw7+d8 incl @rw0+d16 incl @rw1+d16 incl @rw2+d16 incl @rw3+d16 incl @rw0+rw7 incl @rw1+rw7 incl @pc+d16 incl addr16 decl @rw0+d8 decl @rw1+d8 decl @rw2+d8 decl @rw3+d8 decl @rw4+d8 decl @rw5+d8 decl @rw6+d8 decl @rw7+d8 decl @rw0+d16 decl @rw1+d16 decl @rw2+d16 decl @rw3+d16 decl @rw0+rw7 decl @rw1+rw7 decl @pc+d16 decl addr16 movl a, @rw0+d8 movl a, @rw1+d8 movl a, @rw2+d8 movl a, @rw3+d8 movl a, @rw4+d8 movl a, @rw5+d8 movl a, @rw6+d8 movl a, @rw7+d8 movl a, @rw0+d16 movl a, @rw1+d16 movl a, @rw2+d16 movl a, @rw3+d16 movl a, @rw0+rw7 movl a, @rw1+rw7 movl a, @pc+d16 movl a, addr16 movl @r w0+d8, a movl @r w1+d8, a movl @r w2+d8, a movl @r w3+d8, a movl @r w4+d8, a movl @r w5+d8, a movl @r w6+d8, a movl @r w7+d8, a movl @r w0+d16, a movl @r w1+d16, a movl @r w2+d16, a movl @r w3+d16, a movl @r w0+rw7, a movl @r w1+rw7, a movl @p c+d16, a movl addr16, a mov @r w0+d8, #8 mov @r w1+d8, #8 mov @r w2+d8, #8 mov @r w3+d8, #8 mov @r w4+d8, #8 mov @r w5+d8, #8 mov @r w6+d8, #8 mov @r w7+d8, #8 mov @r w0+d16, #8 mov @r w1+d16, #8 mov @r w2+d16, #8 mov @r w3+d16, #8 mov @r w0+rw7, #8 mov @r w1+rw7, #8 mov @p c+d16, #8 mov addr16, #8 movea a, @rw0+d8 movea a, @rw1+d8 movea a, @rw2+d8 movea a, @rw3+d8 movea a, @rw4+d8 movea a, @rw5+d8 movea a, @rw6+d8 movea a, @rw7+d8 movea a, @rw0+d16 movea a, @rw1+d16 movea a, @rw2+d16 movea a, @rw3+d16 movea a, @rw0+rw7 movea a, @rw1+rw7 movea a, @pc+d16 movea a, addr16 b.3 instruction map 342 appendix b: instructions MB90580 series table b.3.1g ea instructions 3 (first byte = 72 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 rolc r0 rolc r1 rolc r2 rolc r3 rolc r4 rolc r5 rolc r6 rolc r7 rolc @rw0 rolc @rw1 rolc @rw2 rolc @rw3 rolc @rw0+ rolc @rw1+ rolc @rw2+ rolc @rw3+ rolc @rw0+d8 rolc @rw1+d8 rolc @rw2+d8 rolc @rw3+d8 rolc @rw4+d8 rolc @rw5+d8 rolc @rw6+d8 rolc @rw7+d8 rolc @rw0+d16 rolc @rw1+d16 rolc @rw2+d16 rolc @rw3+d16 rolc @rw0+rw7 rolc @rw1+rw7 rolc @pc+d16 rolc addr16 rorc r0 rorc r1 rorc r2 rorc r3 rorc r4 rorc r5 rorc r6 rorc r7 rorc @rw0 rorc @rw1 rorc @rw2 rorc @rw3 rorc @rw0+ rorc @rw1+ rorc @rw2+ rorc @rw3+ inc r0 inc r1 inc r2 inc r3 inc r4 inc r5 inc r6 inc r7 inc @rw0 inc @rw1 inc @rw2 inc @rw3 inc @rw0+ inc @rw1+ inc @rw2+ inc @rw3+ dec r0 dec r1 dec r2 dec r3 dec r4 dec r5 dec r6 dec r7 dec @rw0 dec @rw1 dec @rw2 dec @rw3 dec @rw0+ dec @rw1+ dec @rw2+ dec @rw3+ mov a, r0 mov a, r1 mov a, r2 mov a, r3 mov a, r4 mov a, r5 mov a, r6 mov a, r7 mov a, @rw0 mov a, @rw1 mov a, @rw2 mov a, @rw3 mov a, @rw0+ mov a, @rw1+ mov a, @rw2+ mov a, @rw3+ mov r0, a mov r1, a mov r2, a mov r3, a mov r4, a mov r5, a mov r6, a mov r7, a mov @rw0, a mov @rw1, a mov @rw2, a mov @rw3, a mov @rw0+, a mov @rw1+, a mov @rw2+, a mov @rw3+, a movx a, r0 movx a, r1 movx a, r2 movx a, r3 movx a, r4 movx a, r5 movx a, r6 movx a, r7 movx a, @rw0 movx a, @rw1 movx a, @rw2 movx a, @rw3 movx a, @rw0+ movx a, @rw1+ movx a, @rw2+ movx a, @rw3+ xch a, r0 xch a, r1 xch a, r2 xch a, r3 xch a, r4 xch a, r5 xch a, r6 xch a, r7 xch a, @rw0 xch a, @rw1 xch a, @rw2 xch a, @rw3 xch a, @rw0+ xch a, @rw1+ xch a, @rw2+ xch a, @rw3+ rorc @rw0+d8 rorc @rw1+d8 rorc @rw2+d8 rorc @rw3+d8 rorc @rw4+d8 rorc @rw5+d8 rorc @rw6+d8 rorc @rw7+d8 rorc @rw0+d16 rorc @rw1+d16 rorc @rw2+d16 rorc @rw3+d16 rorc @rw0+rw7 rorc @rw1+rw7 rorc @pc+d16 rorc addr16 inc @rw0+d8 inc @rw1+d8 inc @rw2+d8 inc @rw3+d8 inc @rw4+d8 inc @rw5+d8 inc @rw6+d8 inc @rw7+d8 inc @rw0+d16 inc @rw1+d16 inc @rw2+d16 inc @rw3+d16 inc @rw0+rw7 inc @rw1+rw7 inc @pc+d16 inc addr16 dec @rw0+d8 dec @rw1+d8 dec @rw2+d8 dec @rw3+d8 dec @rw4+d8 dec @rw5+d8 dec @rw6+d8 dec @rw7+d8 dec @rw0+d16 dec @rw1+d16 dec @rw2+d16 dec @rw3+d16 dec @rw0+rw7 dec @rw1+rw7 dec @pc+d16 dec addr16 mov a, @rw0+d8 mov a, @rw1+d8 mov a, @rw2+d8 mov a, @rw3+d8 mov a, @rw4+d8 mov a, @rw5+d8 mov a, @rw6+d8 mov a, @rw7+d8 mov a, @rw0+d16 mov a, @rw1+d16 mov a, @rw2+d16 mov a, @rw3+d16 mov a, @rw0+rw7 mov a, @rw1+rw7 mov a, @pc+d16 mov a, addr16 mov @r w0+d8, a mov @r w1+d8, a mov @r w2+d8, a mov @r w3+d8, a mov @r w4+d8, a mov @r w5+d8, a mov @r w6+d8, a mov @r w7+d8, a mov @r w0+d16, a mov @r w1+d16, a mov @r w2+d16, a mov @r w3+d16, a mov @r w0+rw7, a mov @r w1+rw7, a mov @p c+d16, a mov addr16, a movx a, @rw0+d8 movx a, @rw1+d8 movx a, @rw2+d8 movx a, @rw3+d8 movx a, @rw4+d8 movx a, @rw5+d8 movx a, @rw6+d8 movx a, @rw7+d8 movx a, @rw0+d16 movx a, @rw1+d16 movx a, @rw2+d16 movx a, @rw3+d16 movx a, @rw0+rw7 movx a, @rw1+rw7 movx a, @pc+d16 movx a, addr16 xch a, @rw0+d8 xch a, @rw1+d8 xch a, @rw2+d8 xch a, @rw3+d8 xch a, @rw4+d8 xch a, @rw5+d8 xch a, @rw6+d8 xch a, @rw7+d8 xch a, @rw0+d16 xch a, @rw1+d16 xch a, @rw2+d16 xch a, @rw3+d16 xch a, @rw0+rw7 xch a, @rw1+rw7 xch a, @pc+d16 xch a, addr16 b.3 instruction map MB90580 series appendix b: instructions 343 table b.3.1h ea instructions 4 (first byte = 73 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 jmp @rw0 jmp @rw1 jmp @rw2 jmp @rw3 jmp @rw4 jmp @rw5 jmp @rw6 jmp @rw7 jmp @@rw0 jmp @@rw1 jmp @@rw2 jmp @@rw3 jmp @@rw0+ jmp @@rw1+ jmp @@rw2+ jmp @@rw3+ jmp @@rw0+d8 jmp @@rw1+d8 jmp @@rw2+d8 jmp @@rw3+d8 jmp @@rw4+d8 jmp @@rw5+d8 jmp @@rw6+d8 jmp @@rw7+d8 jmp @@rw0+d16 jmp @@rw1+d16 jmp @@rw2+d16 jmp @@rw3+d16 jmp @@rw0+rw7 jmp @@rw1+rw7 jmp @@pc+d16 jmp @addr16 call @rw0 call @rw1 call @rw2 call @rw3 call @rw4 call @rw5 call @rw6 call @rw7 call @@rw0 call @@rw1 call @@rw2 call @@rw3 call @@rw0+ call @@rw1+ call @@rw2+ call @@rw3+ incw rw0 incw rw1 incw rw2 incw rw3 incw rw4 incw rw5 incw rw6 incw rw7 incw @rw0 incw @rw1 incw @rw2 incw @rw3 incw @rw0+ incw @rw1+ incw @rw2+ incw @rw3+ decw rw0 decw rw1 decw rw2 decw rw3 decw rw4 decw rw5 decw rw6 decw rw7 decw @rw0 decw @rw1 decw @rw2 decw @rw3 decw @rw0+ decw @rw1+ decw @rw2+ decw @rw3+ movw a, rw0 movw a, rw1 movw a, rw2 movw a, rw3 movw a, rw4 movw a, rw5 movw a, rw6 movw a, rw7 movw a, @rw0 movw a, @rw1 movw a, @rw2 movw a, @rw3 movw a, @rw0+ movw a, @rw1+ movw a, @rw2+ movw a, @rw3+ movw rw0, a movw rw1, a movw rw2, a movw rw3, a movw rw4, a movw rw5, a movw rw6, a movw rw7, a movw @rw0, a movw @rw1. a movw @rw2, a movw @rw3, a movw @rw0+, a movw @rw1+, a movw @rw2+, a movw @rw3+, a movw rw0, #16 movw rw1, #16 movw rw2, #16 movw rw3, #16 movw rw4, #16 movw rw5, #16 movw rw6, #16 movw rw7, #16 movw @rw0, #16 movw @rw1, #16 movw @rw2, #16 movw @rw3, #16 movw @ rw0+, #16 movw @ rw1+, #16 movw @ rw2+, #16 movw @ rw3+, #16 xchw a, rw0 xchw a, rw1 xchw a, rw2 xchw a, rw3 xchw a, rw4 xchw a, rw5 xchw a, rw6 xchw a, rw7 xchw a, @rw0 xchw a, @rw1 xchw a, @rw2 xchw a, @rw3 xchw a, @rw0+ xchw a, @rw1+ xchw a, @rw2+ xchw a, @rw3+ call @@rw0+d8 call @@rw1+d8 call @@rw2+d8 call @@rw3+d8 call @@rw4+d8 call @@rw5+d8 call @@rw6+d8 call @@rw7+d8 call @@rw0+d16 call @@rw1+d16 call @@rw2+d16 call @@rw3+d16 call @ @rw0+rw7 call @ @rw1+rw7 call call @addr16 incw @rw0+d8 incw @rw1+d8 incw @rw2+d8 incw @rw3+d8 incw @rw4+d8 incw @rw5+d8 incw @rw6+d8 incw @rw7+d8 incw @rw0+d16 incw @rw1+d16 incw @rw2+d16 incw @rw3+d16 incw @rw0+rw7 incw @rw1+rw7 incw @pc+d16 incw addr16 decw @rw0+d8 decw @rw1+d8 decw @rw2+d8 decw @rw3+d8 decw @rw4+d8 decw @rw5+d8 decw @rw6+d8 decw @rw7+d8 decw @rw0+d16 decw @rw1+d16 decw @rw2+d16 decw @rw3+d16 decw @rw0+rw7 decw @rw1+rw7 decw @pc+d16 decw addr16 movw a, @rw0+d8 movw a, @rw1+d8 movw a, @rw2+d8 movw a, @rw3+d8 movw a, @rw4+d8 movw a, @rw5+d8 movw a, @rw6+d8 movw a, @rw7+d8 movw a, @rw0+d16 movw a, @rw1+d16 movw a, @rw2+d16 movw a, @rw3+d16 movw a, @rw0+rw7 movw a, @rw1+rw7 movw a, @pc+d16 movw a, addr16 movw @r w0+d8, a movw @r w1+d8, a movw @r w2+d8, a movw @r w3+d8, a movw @r w4+d8, a movw @r w5+d8, a movw @r w6+d8, a movw @r w7+d8, a movw @r w0+d16, a movw @r w1+d16, a movw @r w2+d16, a movw @r w3+d16, a movw @r w0+rw7, a movw @r w1+rw7, a movw @p c+d16, a movw addr16, a movw @rw 0+d8, #16 movw @rw 1+d8, #16 movw @rw 2+d8, #16 movw @rw 3+d8, #16 movw @rw 4+d8, #16 movw @rw 5+d8, #16 movw @rw 6+d8, #16 movw @rw 7+d8, #16 movw@rw0 +d16, #16 movw@rw1 +d16, #16 movw@ rw2 +d16, #16 movw @rw3 +d16, #16 movw@rw0 +rw7, #16 movw @rw1 +rw7, #16 movw @pc +d16, #16 movw ad dr16, #16 xchw a, @rw0+d8 xchw a, @rw1+d8 xchw a, @rw2+d8 xchw a, @rw3+d8 xchw a, @rw4+d8 xchw a, @rw5+d8 xchw a, @rw6+d8 xchw a, @rw7+d8 xchw a, @rw0+d16 xchw a, @rw1+d16 xchw a, @rw2+d16 xchw a, @rw3+d16 xchw a, @rw0+rw7 xchw a, @rw1+rw7 xchw a, @pc+d16 xchw a, addr16 @@pc+d16 b.3 instruction map 344 appendix b: instructions MB90580 series table b.3.1i ea instructions 5 (first byte = 74 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 add a, r0 add a, r1 add a, r2 add a, r3 add a, r4 add a, r5 add a, r6 add a, r7 add a, @rw0 add a, @rw1 add a, @rw2 add a, @rw3 add a, @rw0+ add a, @rw1+ add a, @rw2+ add a, @rw3+ add a, @rw0+d8 add a, @rw1+d8 add a, @rw2+d8 add a, @rw3+d8 add a, @rw4+d8 add a, @rw5+d8 add a, @rw6+d8 add a, @rw7+d8 add a, @rw0+d16 add a, @rw1+d16 add a, @rw2+d16 add a, @rw3+d16 add a, @rw0+rw7 add a, @rw1+rw7 add a, @pc+d16 add a, addr16 sub a, r0 sub a, r1 sub a, r2 sub a, r3 sub a, r4 sub a, r5 sub a, r6 sub a, r7 sub a, @rw0 sub a, @rw1 sub a, @rw2 sub a, @rw3 sub a, @rw0+ sub a, @rw1+ sub a, @rw2+ sub a, @rw3+ addc a, r0 addc a, r1 addc a, r2 addc a, r3 addc a, r4 addc a, r5 addc a, r6 addc a. r7 addc a, @rw0 addc a, @rw1 addc a, @rw2 addc a, @rw3 addc a, @rw0+ addc a, @rw1+ addc a, @rw2+ addc a, @rw3+ cmp a, r0 cmp a, r1 cmp a, r2 cmp a, r3 cmp a, r4 cmp a, r5 cmp a, r6 cmp a, r7 cmp a, @rw0 cmp a, @rw1 cmp a, @rw2 cmp a, @rw3 cmp a, @rw0+ cmp a, @rw1+ cmp a, @rw2+ cmp a, @rw3+ and a, r0 and a, r1 and a, r2 and a, r3 and a, r4 and a, r5 and a, r6 and a, r7 and a, @rw0 and a, @rw1 and a, @rw2 and a, @rw3 and a, @rw0+ and a, @rw1+ and a, @rw2+ and a, @rw3+ or a, r0 or a, r1 or a, r2 or a, r3 or a, r4 or a, r5 or a, r6 or a, r7 or a, @rw0 or a, @rw1 or a, @rw2 or a, @rw3 or a, @rw0+ or a, @rw1+ or a, @rw2+ or a, @rw3+ xor a, r0 xor a, r1 xor a, r2 xor a, r3 xor a, r4 xor a, r5 xor a, r6 xor a, r7 xor a, @rw0 xor a, @rw1 xor a, @rw2 xor a, @rw3 xor a, @rw0+ xor a, @rw1+ xor a, @rw2+ xor a, @rw3+ dbnz r0, r dbnz r1, r dbnz r2, r dbnz r3, r dbnz r4, r dbnz r5, r dbnz r6, r dbnz r7, r dbnz @rw0, r dbnz @rw1, r dbnz @rw2, r dbnz @rw3, r dbnz @rw0+, r dbnz @rw1+, r dbnz @rw2+, r dbnz @rw3+, r sub a, @rw0+d8 sub a, @rw1+d8 sub a, @rw2+d8 sub a, @rw3+d8 sub a, @rw4+d8 sub a, @rw5+d8 sub a, @rw6+d8 sub a, @rw7+d8 sub a, @rw0+d16 sub a, @rw1+d16 sub a, @rw2+d16 sub a, @rw3+d16 sub a, @rw0+rw7 sub a, @rw1+rw7 sub a, sub a, addr16 addc a, @rw0+d8 addc a, @rw1+d8 addc a, @rw2+d8 addc a, @rw3+d8 addc a, @rw4+d8 addc a, @rw5+d8 addc a, @rw6+d8 addc a, @rw7+d8 addc a, @rw0+d16 addc a, @rw1+d16 addc a, @rw2+d16 addc a, @rw3+d16 addc a, @rw0+rw7 addc a, @rw1+rw7 addc a, @pc+d16 addc a, addr16 cmp a, @rw0+d8 cmp a, @rw1+d8 cmp a, @rw2+d8 cmp a, @rw3+d8 cmp a, @rw4+d8 cmp a, @rw5+d8 cmp a, @rw6+d8 cmp a, @rw7+d8 cmp a, @rw0+d16 cmp a, @rw1+d16 cmp a, @rw2+d16 cmp a, @rw3+d16 cmp a, @rw0+rw7 cmp a, @rw1+rw7 cmp a, @pc+d16 cmp a, addr16 and a, @rw0+d8 and a, @rw1+d8 and a, @rw2+d8 and a, @rw3+d8 and a, @rw4+d8 and a, @rw5+d8 and a, @rw6+d8 and a, @rw7+d8 and a, @rw0+d16 and a, @rw1+d16 and a, @rw2+d16 and a, @rw3+d16 and a, @rw0+rw7 and a, @rw1+rw7 and a, @pc+d16 and a, addr16 or a, @rw0+d8 or a, @rw1+d8 or a, @rw2+d8 or a, @rw3+d8 or a, @rw4+d8 or a, @rw5+d8 or a, @rw6+d8 or a, @rw7+d8 or a, @rw0+d16 or a, @rw1+d16 or a, @rw2+d16 or a, @rw3+d16 or a, @rw0+rw7 or a, @rw1+rw7 or a, @ pc+d16 or a, addr16 xor a, @rw0+d8 xor a, @rw1+d8 xor a, @rw2+d8 xor a, @rw3+d8 xor a, @rw4+d8 xor a, @rw5+d8 xor a, @rw6+d8 xor a, @rw7+d8 xor a, @rw0+d16 xor a, @rw1+d16 xor a, @rw2+d16 xor a, @rw3+d16 xor a, @rw0+rw7 xor a, @rw1+rw7 xor a, @pc+d16 xor a, addr16 dbnz @ rw0+d8, r dbnz @ rw1+d8, r dbnz @ rw2+d8, r dbnz @ rw3+d8, r dbnz @ rw4+d8, r dbnz @ rw5+d8, r dbnz @ rw6+d8, r dbnz @ rw7+d8, r dbnz rw0+d16, r dbnz rw1+d16, r dbnz rw2+d16, r dbnz rw3+d16, r dbnz rw0+rw7, r dbnz rw1+rw7, r dbnz @ pc+d16, r dbnz @ addr16, r @pc+d16 b.3 instruction map MB90580 series appendix b: instructions 345 table b.3.1j ea instructions 6 (first byte = 75 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 add r0, a add r1, a add r2, a add r3, a add r4, a add r5, a add r6, a add r7, a add @rw0, a add @rw1, a add @rw2, a add @rw3, a add @rw0+, a add @rw1+, a add @rw2+, a add @rw3+, a w0+d8, a w1+d8, a w2+d8, a w3+d8, a w4+d8, a w5+d8, a w6+d8, a w7+d8, a w0+d16, a w1+d16, a rw2+d16, a rw3+d16, a add @r w0+rw7, a add @r w1+rw7, a c+d16, a add addr16, a sub r0, a sub r1, a sub r2, a sub r3, a sub r4, a sub r5, a sub r6, a sub r7, a sub @rw0, a sub @rw1, a sub @rw2, a sub @rw3, a sub @rw0+, a sub @rw1+, a sub @rw2+, a sub @rw3+, a subc a, r0 subc a, r1 subc a, r2 subc a, r3 subc a, r4 subc a, r5 subc a, r6 subc a, r7 subc a, @rw0 subc a, @rw1 subc a, @rw2 subc a, @rw3 subc a, @rw0+ subc a, @rw1+ subc a, @rw2+ subc a, @rw3+ neg r0 neg r1 neg r2 neg r3 neg r4 neg r5 neg r6 neg r7 neg @rw0 neg @rw1 neg @rw2 neg @rw3 neg @rw0+ neg @rw1+ neg @rw2+ neg @rw3+ and r0, a and r1, a and r2, a and r3, a and r4, a and r5, a and r6, a and r7, a and @rw0, a and @rw1, a and @rw2, a and @rw3, a and @rw0+, a and @rw1+, a and @rw2+, a and @rw3+, a or r0, a or r1, a or r2, a or r3, a or r4, a or r5, a or r6, a or r7, a or @rw0, a or @rw1, a or @rw2, a or @rw3, a or @rw0+, a or @rw1+, a or @rw2+, a or @rw3+, a xor r0, a xor r1, a xor r2, a xor r3, a xor r4, a xor r5, a xor r6, a xor r7, a xor @rw0, a xor @rw1, a xor @rw2, a xor @rw3, a xor @rw0+, a xor @rw1+, a xor @rw2+, a xor @rw3+, a not r0 not r1 not r2 not r3 not r4 not r5 not r6 not r7 not @rw0 not @rw1 not @rw2 not @rw3 not @rw0+ not @rw1+ not @rw2+ not @rw3+ sub @r w0+d8, a sub @r w1+d8, a sub @r w2+d8, a sub @r w3+d8, a sub @r w4+d8, a sub @r w5+d8, a sub @r w6+d8, a sub @r w7+d8, a sub @r w0+d16, a sub @r w1+d16, a sub @r w2+d16, a sub @r w3+d16, a sub @r w0+rw7, a sub @r w1+rw7, a sub @p sub addr16, a subc a, @rw0+d8 subc a, @rw1+d8 subc a, @rw2+d8 subc a, @rw3+d8 subc a, @rw4+d8 subc a, @rw5+d8 subc a, @rw6+d8 subc a, @rw7+d8 subc a, @rw0+d16 subc a, @rw1+d16 subc a, @rw2+d16 subc a, @rw3+d16 subc a, @rw0+rw7 subc a, @rw1+rw7 subc a, @pc+d16 subc a, addr16 neg @rw0+d8 neg @rw1+d8 neg @rw2+d8 neg @rw3+d8 neg @rw4+d8 neg @rw5+d8 neg @rw6+d8 neg @rw7+d8 neg @rw0+d16 neg @rw1+d16 neg @rw2+d16 neg @rw3+d16 neg @rw0+rw7 neg @rw1+rw7 neg @pc+d16 neg addr16 and @r w0+d8, a and @r w1+d8, a and @r w2+d8, a and @r w3+d8, a and @r w4+d8, a and @r w5+d8, a and @r w6+d8, a and @r w7+d8, a and @r w0+d16, a and @r w1+d16, a and @r w2+d16, a and @r w3+d16, a and @r w0+rw7, a and @r w1+rw7, a and @p c+d16, a and addr16, a or @rw0+d8, a or @rw1+d8, a or @rw2+d8, a or @rw3+d8, a or @rw4+d8, a or @rw5+d8, a or @rw6+d8, a or @rw7+d8, a or @rw0+d16, a or @rw1+d16, a or @rw2+d16, a or @rw3+d16, a or @r w0+rw7, a or @r w1+rw7, a or @pc+d16, a or addr16, a w0+d8, a w1+d8, a w2+d8, a w3+d8, a w4+d8, a w5+d8, a w6+d8, a w7+d8, a w0+d16, a w1+d16, a w2+d16, a w3+d16, a xor @r w0+rw7, a xor @r w1+rw7, a c+d16, a xor addr16, a not @rw0+d8 not @rw1+d8 not @rw2+d8 not @rw3+d8 not @rw4+d8 not @rw5+d8 not @rw6+d8 not @rw7+d8 not @rw0+d16 not @rw1+d16 not @rw2+d16 not @rw3+d16 not @rw0+rw7 not @rw1+rw7 not @pc+d16 not addr16 c+d16, a add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @p xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @p b.3 instruction map 346 appendix b: instructions MB90580 series table b.3.1k ea instructions 7 (first byte = 76 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 addw a, rw0 addw a, rw1 addw a, rw2 addw a, rw3 addw a, rw4 addw a, rw5 addw a, rw6 addw a, rw7 addw a, @rw0 addw a, @rw1 addw a, @rw2 addw a, @rw3 addw a, @rw0+ addw a, @rw1+ addw a, @rw2+ addw a, @rw3+ addw a, @rw0+d8 addw a, @rw1+d8 addw a, @rw2+d8 addw a, @rw3+d8 addw a, @rw4+d8 addw a, @rw5+d8 addw a, @rw6+d8 addw a, @rw7+d8 addw a, @rw0+d16 addw a, @rw1+d16 addw a, @rw2+d16 addw a, @rw3+d16 addw a, @rw0+rw7 addw a, @rw1+rw7 addw a, @pc+d16 addw a, addr16 subw a, rw0 subw a, rw1 subw a, rw2 subw a, rw3 subw a, rw4 subw a, rw5 subw a, rw6 subw a, rw7 subw a, @rw0 subw a, @rw1 subw a, @rw2 subw a, @rw3 subw a, @rw0+ subw a, @rw1+ subw a, @rw2+ subw a, @rw3+ addcw a, rw0 addcw a, rw1 addcw a, rw2 addcw a, rw3 addcw a, rw4 addcw a, rw5 addcw a, rw6 addcw a, rw7 addcw a, @rw0 addcw a, @rw1 addcw a, @rw2 addcw a, @rw3 addcw a, @rw0+ addcw a, @rw1+ addcw a, @rw2+ addcw a, @rw3+ cmpw a, rw0 cmpw a, rw1 cmpw a, rw2 cmpw a, rw3 cmpw a, rw4 cmpw a, rw5 cmpw a, rw6 cmpw a, rw7 cmpw a, @rw0 cmpw a, @rw1 cmpw a, @rw2 cmpw a, @rw3 cmpw a, @rw0+ cmpw a, @rw1+ cmpw a, @rw2+ cmpw a, @rw3+ andw a, rw0 andw a, rw1 andw a, rw2 andw a, rw3 andw a, rw4 andw a, rw5 andw a, rw6 andw a, rw7 andw a, @rw0 andw a, @rw1 andw a, @rw2 andw a, @rw3 andw a, @rw0+ andw a, @rw1+ andw a, @rw2+ andw a, @rw3+ orw a, rw0 orw a, rw1 orw a, rw2 orw a, rw3 orw a, rw4 orw a, rw5 orw a, rw6 orw a, rw7 orw a, @rw0 orw a, @rw1 orw a, @rw2 orw a, @rw3 orw a, @rw0+ orw a, @rw1+ orw a, @rw2+ orw a, @rw3+ xorw a, rw0 xorw a, rw1 xorw a, rw2 xorw a, rw3 xorw a, rw4 xorw a, rw5 xorw a, rw6 xorw a, rw7 xorw a, @rw0 xorw a, @rw1 xorw a, @rw2 xorw a, @rw3 xorw a, @rw0+ xorw a, @rw1+ xorw a, @rw2+ xorw a, @rw3+ dwbnz rw0, r dwbnz rw1, r dwbnz rw2, r dwbnz rw3, r dwbnz rw4, r dwbnz rw5, r dwbnz rw6, r dwbnz rw7, r dwbnz @rw0, r dwbnz @rw1, r dwbnz @rw2, r dwbnz @rw3, r dwbnz @rw0+, r dwbnz @rw1+, r dwbnz @rw2+, r dwbnz @rw3+, r subw a, @rw0+d8 subw a, @rw1+d8 subw a, @rw2+d8 subw a, @rw3+d8 subw a, @rw4+d8 subw a, @rw5+d8 subw a, @rw6+d8 subw a, @rw7+d8 subw a, @rw0+d16 subw a, @rw1+d16 subw a, @rw2+d16 subw a, @rw3+d16 subw a, @rw0+rw7 subw a, @rw1+rw7 subw a, subw a, addr16 addcw a, @rw0+d8 addcw a, @rw1+d8 addcw a, @rw2+d8 addcw a, @rw3+d8 addcw a, @rw4+d8 addcw a, @rw5+d8 addcw a, @rw6+d8 addcw a, @rw7+d8 addcw a, @rw0+d16 addcw a, @rw1+d16 addcw a, @rw2+d16 addcw a, @rw3+d16 addcw a, @rw0+rw7 addcw a, @rw1+rw7 addcw a, @pc+d16 addcw a, addr16 cmpw a, @rw0+d8 cmpw a, @rw1+d8 cmpw a, @rw2+d8 cmpw a, @rw3+d8 cmpw a, @rw4+d8 cmpw a, @rw5+d8 cmpw a, @rw6+d8 cmpw a, @rw7+d8 cmpw a, @rw0+d16 cmpw a, @rw1+d16 cmpw a, @rw2+d16 cmpw a, @rw3+d16 cmpw a, @rw0+rw7 cmpw a, @rw1+rw7 cmpw a, @pc+d16 cmpw a, addr16 andw a, @rw0+d8 andw a, @rw1+d8 andw a, @rw2+d8 andw a, @rw3+d8 andw a, @rw4+d8 andw a, @rw5+d8 andw a, @rw6+d8 andw a, @rw7+d8 andw a, @rw0+d16 andw a, @rw1+d16 andw a, @rw2+d16 andw a, @rw3+d16 andw a, @rw0+rw7 andw a, @rw1+rw7 andw a, @pc+d16 andw a, addr16 orw a, @rw0+d8 orw a, @rw1+d8 orw a, @rw2+d8 orw a, @rw3+d8 orw a, @rw4+d8 orw a, @rw5+d8 orw a, @rw6+d8 orw a, @rw7+d8 orw a, @rw0+d16 orw a, @rw1+d16 orw a, @rw2+d16 orw a, @rw3+d16 orw a, @rw0+rw7 orw a, @rw1+rw7 orw a, @ pc+d16 orw a, addr16 xorw a, @rw0+d8 xorw a, @rw1+d8 xorw a, @rw2+d8 xorw a, @rw3+d8 xorw a, @rw4+d8 xorw a, @rw5+d8 xorw a, @rw6+d8 xorw a, @rw7+d8 xorw a, @rw0+d16 xorw a, @rw1+d16 xorw a, @rw2+d16 xorw a, @rw3+d16 xorw a, @rw0+rw7 xorw a, @rw1+rw7 xorw a, @pc+d16 xorw a, addr16 dwbnz @ rw0+d8, r dwbnz @ rw1+d8, r dwbnz @ rw2+d8, r dwbnz @ rw3+d8, r dwbnz @ rw4+d8, r dwbnz @ rw5+d8, r dwbnz @ rw6+d8, r dwbnz @ rw7+d8, r dwbnz @r w0+d16, r dwbnz @r w1+d16, r dwbnz @r w2+d16, r dwbnz @r w3+d16, r dwbnz @r w0+rw7, r dwbnz @r w1+rw7, r dwbnz @ pc+d16, r dwbnz addr16, r @pc+d16 b.3 instruction map MB90580 series appendix b: instructions 347 table b.3.1l ea instructions 8 (first byte = 77 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 addw rw0, a addw rw1, a addw rw2, a addw rw3, a addw rw4, a addw rw5, a addw rw6, a addw rw7, a addw @rw0, a addw @rw1, a addw @rw2, a addw @rw3, a addw @rw0+, a addw @rw1+, a addw @rw2+, a addw @rw3+, a addw @r w0+d8, a addw @r w1+d8, a addw @r w2+d8, a addw @r w3+d8, a addw @r w4+d8, a addw @r w5+d8, a addw @r w6+d8, a addw @r w7+d8, a addw @r w0+d16, a addw @r w1+d16, a addw @r w2+d16, a addw @r w3+d16, a addw @r w0+rw7 addw @r w1+rw7 addw @p c+d16, a addw addr16, a subw rw0, a subw rw1, a subw rw2, a subw rw3, a subw rw4, a subw rw5, a subw rw6, a subw rw7, a subw @rw0, a subw @rw1, a subw @rw2, a subw @rw3, a subw @rw0+, a subw @rw1+, a subw @rw2+, a subw @rw3+, a subcw a, rw0 subcw a, rw1 subcw a, rw2 subcw a, rw3 subcw a, rw4 subcw a, rw5 subcw a, rw6 subcw a,rw7 subcw a, @rw0 subcw a, @rw1 subcw a, @rw2 subcw a, @rw3 subcw a, @rw0+ subcw a, @rw1+ subcw a, @rw2+ subcw a, @rw3+ negw rw0 negw rw1 negw rw2 negw rw3 negw rw4 negw rw5 negw rw6 negw rw7 negw @rw0 negw @rw1 negw @rw2 negw @rw3 negw @rw0+ negw @rw1+ negw @rw2+ negw @rw3+ andw rw0, a andw rw1, a andw rw2, a andw rw3, a andw rw4, a andw rw5, a andw rw6, a andw rw7, a andw @rw0, a andw @rw1, a andw @rw2, a andw @rw3, a andw @rw0+, a andw @rw1+, a andw @rw2+, a andw @rw3+, a orw rw0, a orw rw1, a owr rw2, a orw rw3, a orw rw4, a orw rw5, a orw rw6, a orw rw7, a orw @rw0, a orw @rw1, a orw @rw2, a orw @rw3, a orw @rw0+, a orw @rw1+, a orw @rw2+, a orw @rw3+, a xorw rw0, a xorw rw1, a xorw rw2, a xorw rw3, a xorw rw4, a xorw rw5, a xorw rw6, a xorw rw7, a xorw @rw0, a xorw @rw1, a xorw @rw2, a xorw @rw3, a xorw @rw0+, a xorw @rw1+, a xorw @rw2+, a xorw @rw3+, a notw rw0 notw rw1 notw rw2 notw rw3 notw rw4 notw rw5 notw rw6 notw rw7 notw @rw0 notw @rw1 notw @rw2 notw @rw3 notw @rw0+ notw @rw1+ notw @rw2+ notw @rw3+ subw @r w0+d8, a subw @r w1+d8, a subw @r w2+d8, a subw @r w3+d8, a subw @r w4+d8, a subw @r w5+d8, a subw @r w6+d8, a subw @r w7+d8, a subw @r w0+d16, a subw @r w1+d16, a subw @r w2+d16, a subw @r w3+d16, a subw @r w0+rw7, a subw @r w1+rw7, a subw subw addr16, a subcw a, @rw0+d8 subcw a, @rw1+d8 subcw a, @rw2+d8 subcw a, @rw3+d8 subcw a, @rw4+d8 subcw a, @rw5+d8 subcw a, @rw6+d8 subcw a, @rw7+d8 subcw a, @rw0+d16 subcw a, @rw1+d16 subcw a, @rw2+d16 subcw a, @rw3+d16 subcw a, @rw0+rw7 subcw a, @rw1+rw7 subcw a, @pc+d16 subcw a, addr16 negw @rw0+d8 negw @rw1+d8 negw @rw2+d8 negw @rw3+d8 negw @rw4+d8 negw @rw5+d8 negw @rw6+d8 negw @rw7+d8 negw @rw0+d16 negw @rw1+d16 negw @rw2+d16 negw @rw3+d16 negw @rw0+rw7 negw @rw1+rw7 negw @pc+d16 negw addr16 andw @r w0+d8, a andw @r w1+d8, a andw @r w2+d8, a andw @r w3+d8, a andw @r w4+d8, a andw @r w5+d8, a andw @r w6+d8, a andw @r w7+d8, a andw @r w0+d16, a andw @r w1+d16, a andw @r w2+d16, a andw @r w3+d16, a andw @r w0+rw7, a andw @r w1+rw7, a andw @p c+d16, a andw addr16, a orw @r w0+d8, a orw @r w1+d8, a orw @r w2+d8, a orw @r w3+d8, a orw @r w4+d8, a orw @r w5+d8, a orw @r w6+d8, a orw @r w7+d8, a orw @r w0+d16, a orw @r w1+d16, a orw @r w2+d16, a orw @r w3+d16, a orw @r w0+rw7, a orw @r w1+rw7, a c+d16, a orw addr16, a xorw @r w0+d8, a xorw @r w1+d8, a xorw @r w2+d8, a xorw @r w3+d8, a xorw @r w4+d8, a xorw @r w5+d8, a xorw @r w6+d8, a xorw @r w7+d8, a xorw @r w0+d16, a xorw @r w1+d16, a xorw @r w2+d16, a xorw @r w3+d16, a xorw @r w0+rw7, a xorw @r w1+rw7, a xorw @p c+d16, a xorw addr16, a notw @rw0+d8 notw @rw1+d8 notw @rw2+d8 notw @rw3+d8 notw @rw4+d8 notw @rw5+d8 notw @rw6+d8 notw @rw7+d8 notw @rw0+d16 notw @rw1+d16 notw @rw2+d16 notw @rw3+d16 notw @rw0+rw7 notw @rw1+rw7 notw @pc+d16 notw addr16 @pc+d16, a orw @p b.3 instruction map 348 appendix b: instructions MB90580 series table b.3.1m ea instructions 9 (first byte = 78 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 mulu a, r0 mulu a, r1 mulu a, r2 mulu a, r3 mulu a, r4 mulu a, r5 mulu a, r6 mulu a, r7 mulu a, @rw0 mulu a, @rw1 mulu a, @rw2 mulu a, @rw3 mulu a, @rw0+ mulu a, @rw1+ mulu a, @rw2+ mulu a, @rw3+ mulu a, @rw0+d8 mulu a, @rw1+d8 mulu a, @rw2+d8 mulu a, @rw3+d8 mulu a, @rw4+d8 mulu a, @rw5+d8 mulu a, @rw6+d8 mulu a, @rw7+d8 mulu a, @rw0+d16 mulu a, @rw1+d16 mulu a, @rw2+d16 mulu a, @rw3+d16 mulu a, @rw0+rw7 mulu a, @rw1+rw7 mulu a, @pc+d16 mulu a, addr16 muluw a, rw0 muluw a, rw1 muluw a, rw2 muluw a, rw3 muluw a, rw4 muluw a, rw5 muluw a, rw6 muluw a, rw7 muluw a, @rw0 muluw a, @rw1 muluw a, @rw2 muluw a, @rw3 muluw a, @rw0+ muluw a, @rw1+ muluw a, @rw2+ muluw a, @rw3+ divu a, r0 divu a, r1 divu a, r2 divu a, r3 divu a, r4 divu a, r5 divu a, r6 divu a, r7 divu a, @rw0 divu a, @rw1 divu a, @rw2 divu a, @rw3 divu a, @rw0+ divu a, @rw1+ divu a, @rw2+ divu a, @rw3+ divuw a, rw0 divuw a, rw1 divuw a, rw2 divuw a, rw3 divuw a, rw4 divuw a, rw5 divuw a, rw6 divuw a, rw7 divuw a, @rw0 divuw a, @rw1 divuw a, @rw2 divuw a, @rw3 divuw a, @rw0+ divuw a, @rw1+ divuw a, @rw2+ divuw a, @rw3+ muluw a, @rw0+d8 muluw a, @rw1+d8 muluw a, @rw2+d8 muluw a, @rw3+d8 muluw a, @rw4+d8 muluw a, @rw5+d8 muluw a, @rw6+d8 muluw a, @rw7+d8 muluw a, @rw0+d16 muluw a, @rw1+d16 muluw a, @rw2+d16 muluw a, @rw3+d16 muluw a, @rw0+rw7 muluw a, @rw1+rw7 muluw a, muluw a, addr16 divu a, @rw0+d8 divu a, @rw1+d8 divu a, @rw2+d8 divu a, @rw3+d8 divu a, @rw4+d8 divu a, @rw5+d8 divu a, @rw6+d8 divu a, @rw7+d8 divu a, @rw0+d16 divu a, @rw1+d16 divu a, @rw2+d16 divu a, @rw3+d16 divu a, @rw0+rw7 divu a, @rw1+rw7 divu a, @pc+d16 divu a, addr16 divuw a, @rw0+d8 divuw a, @rw1+d8 divuw a, @rw2+d8 divuw a, @rw3+d8 divuw a, @rw4+d8 divuw a, @rw5+d8 divuw a, @rw6+d8 divuw a, @rw7+d8 divuw a, @rw0+d16 divuw a, @rw1+d16 divuw a, @rw2+d16 divuw a, @rw3+d16 divuw a, @rw0+rw7 divuw a, @rw1+rw7 divuw a, @ pc+d16 divuw a, addr16 @pc+d16 mul a, r0 mul a, r1 mul a, r2 mul a, r3 mul a, r4 mul a, r5 mul a, r6 mul a, r7 mul a, @rw0 mul a, @rw1 mul a, @rw2 mul a, @rw3 mul a, @rw0+ mul a, @rw1+ mul a, @rw2+ mul a, @rw3+ mul a, @rw0+d8 mul a, @rw1+d8 mul a, @rw2+d8 mul a, @rw3+d8 mul a, @rw4+d8 mul a, @rw5+d8 mul a, @rw6+d8 mul a, @rw7+d8 mul a, @rw0+d16 mul a, @rw1+d16 mul a, @rw2+d16 mul a, @rw3+d16 mul a, @rw0+rw7 mul a, @rw1+rw7 mul a, @pc+d16 mul a, addr16 mulw a, rw0 mulw a, rw1 mulw a, rw2 mulw a, rw3 mulw a, rw4 mulw a, rw5 mulw a, rw6 mulw a, rw7 mulw a, @rw0 mulw a, @rw1 mulw a, @rw2 mulw a, @rw3 mulw a, @rw0+ mulw a, @rw1+ mulw a, @rw2+ mulw a, @rw3+ mulw a, @rw0+d8 mulw a, @rw1+d8 mulw a, @rw2+d8 mulw a, @rw3+d8 mulw a, @rw4+d8 mulw a, @rw5+d8 mulw a, @rw6+d8 mulw a, @rw7+d8 mulw a, @rw0+d16 mulw a, @rw1+d16 mulw a, @rw2+d16 mulw a, @rw3+d16 mulw a, @rw0+rw7 mulw a, @rw1+rw7 mulw a, mulw a, addr16 @pc+d16 div a, r0 div a, r1 div a, r2 div a, r3 div a, r4 div a, r5 div a, r6 div a, r7 div a, @rw0 div a, @rw1 div a, @rw2 div a, @rw3 div a, @rw0+ div a, @rw1+ div a, @rw2+ div a, @rw3+ div a, @rw0+d8 div a, @rw1+d8 div a, @rw2+d8 div a, @rw3+d8 div a, @rw4+d8 div a, @rw5+d8 div a, @rw6+d8 div a, @rw7+d8 div a, @rw0+d16 div a, @rw1+d16 div a, @rw2+d16 div a, @rw3+d16 div a, @rw0+rw7 div a, @rw1+rw7 div a, @pc+d16 div a, addr16 divw a, rw0 divw a, rw1 divw a, rw2 divw a, rw3 divw a, rw4 divw a, rw5 divw a, rw6 divw a, rw7 divw a, @rw0 divw a, @rw1 divw a, @rw2 divw a, @rw3 divw a, @rw0+ divw a, @rw1+ divw a, @rw2+ divw a, @rw3+ divw a, @rw0+d8 divw a, @rw1+d8 divw a, @rw2+d8 divw a, @rw3+d8 divw a, @rw4+d8 divw a, @rw5+d8 divw a, @rw6+d8 divw a, @rw7+d8 divw a, @rw0+d16 divw a, @rw1+d16 divw a, @rw2+d16 divw a, @rw3+d16 divw a, @rw0+rw7 divw a, @rw1+rw7 divw a, @ pc+d16 divw a, addr16 b.3 instruction map MB90580 series appendix b: instructions 349 table b.3.1n movea rwi, ea (first byte = 79 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 movea rw0, rw0 movea rw0, rw1 movea rw0, rw2 movea rw0, rw3 movea rw0, rw4 movea rw0, rw5 movea rw0, rw6 movea rw0, rw7 movea rw0, @rw0 movea rw0, @rw1 movea rw0, @rw2 movea rw0, @rw3 movea r w0, @rw0+ movea r w0, @rw1+ movea r w0, @rw2+ movea r w0, @rw3+ movea rw0, @rw0+d8 movea rw0, @rw1+d8 movea rw0, @rw2+d8 movea rw0, @rw3+d8 movea rw0, @rw4+d8 movea rw0, @rw5+d8 movea rw0, @rw6+d8 movea rw0, @rw7+d8 movea rw0, @rw0+d16 movea rw0, @rw1+d16 movea rw0, @rw2+d16 movea rw0, @rw3+d16 movea rw0, @rw0+rw7 movea rw0, @rw1+rw7 movea rw0, @pc+d16 movea rw0, addr16 movea rw1, rw0 movea rw1, rw1 movea rw1, rw2 movea rw1, rw3 movea rw1, rw4 movea rw1, rw5 movea rw1, rw6 movea rw1, rw7 movea rw1, @rw0 movea rw1, @rw1 movea rw1, @rw2 movea rw1, @rw3 movea r w1, @rw0+ movea r w1, @rw1+ movea r w1, @rw2+ movea r w1, @rw3+ movea rw2, rw0 movea rw2, rw1 movea rw2, rw2 movea rw2, rw3 movea rw2, rw4 movea rw2, rw5 movea rw2, rw6 movea rw2, rw7 movea rw2, @rw0 movea rw2, @rw1 movea rw2, @rw2 movea rw2, @rw3 movea r w2, @rw0+ movea r w2, @rw1+ movea r w2, @rw2+ movea r w2, @rw3+ movea rw3, rw0 movea rw3, rw1 movea rw3, rw2 movea rw3, rw3 movea rw3, rw4 movea rw3, rw5 movea rw3, rw6 movea rw3, rw7 movea rw3, @rw0 movea rw3, @rw1 movea rw3, @rw2 movea rw3, @rw3 movea r w3, @rw0+ movea r w3, @rw1+ movea r w3, @rw2+ movea r w3, @rw3+ movea rw4, rw0 movea rw4, rw1 movea rw4, rw2 movea rw4, rw3 movea rw4, rw4 movea rw4, rw5 movea rw4, rw6 movea rw4, rw7 movea rw4, @rw0 movea rw4, @rw1 movea rw4, @rw2 movea rw4, @rw3 movea r w4, @rw0+ movea r w4, @rw1+ movea r w4, @rw2+ movea r w4, @rw3+ movea rw5, rw0 movea rw5, rw1 movea rw5, rw2 movea rw5, rw3 movea rw5, rw4 movea rw5, rw5 movea rw5, rw6 movea rw5, rw7 movea rw5, @rw0 movea rw5, @rw1 movea rw5, @rw2 movea rw5, @rw3 movea r w5, @rw0+ movea r w5, @rw1+ movea r w5, @rw2+ movea r w5, @rw3+ movea rw6, rw0 movea rw6, rw1 movea rw6, rw2 movea rw6, rw3 movea rw6, rw4 movea rw6, rw5 movea rw6, rw6 movea rw6, rw7 movea rw6, @rw0 movea rw6, @rw1 movea rw6, @rw2 movea rw6, @rw3 movea r w6, @rw0+ movea r w6, @rw1+ movea r w6, @rw2+ movea w6, @rw3+ movea rw7, rw0 movea rw7, rw1 movea rw7, rw2 movea rw7, rw3 movea rw7, rw4 movea rw7, rw5 movea rw7, rw6 movea rw7, rw7 movea rw7, @rw0 movea rw7, @rw1 movea rw7, @rw2 movea rw7, @rw3 movea r w7, @rw0+ movea r w7, @rw1+ movea r w7, @rw2+ movea r w7, @rw3+ movea rw1, @rw0+d8 movea rw1, @rw1+d8 movea rw1, @rw2+d8 movea rw1, @rw3+d8 movea rw1, @rw4+d8 movea rw1, @rw5+d8 movea rw1, @rw6+d8 movea rw1, @rw7+d8 movea rw1, @rw0+d16 movea rw1, @rw1+d16 movea rw1, @rw2+d16 movea rw1, @rw3+d16 movea rw1, @rw0+rw7 movea rw1, @rw1+rw7 movea rw1, movea rw1, addr16 movea rw2, @rw0+d8 movea rw2, @rw1+d8 movea rw2, @rw2+d8 movea rw2, @rw3+d8 movea rw2, @rw4+d8 movea rw2, @rw5+d8 movea rw2, @rw6+d8 movea rw2, @rw7+d8 movea rw2, @rw0+d16 movea rw2, @rw1+d16 movea rw2, @rw2+d16 movea rw2, @rw3+d16 movea rw2, @rw0+rw7 movea rw2, @rw1+rw7 movea rw2, @pc+d16 movea rw2, addr16 movea rw3, @rw0+d8 movea rw3, @rw1+d8 movea rw3, @rw2+d8 movea rw3, @rw3+d8 movea rw3, @rw4+d8 movea rw3, @rw5+d8 movea rw3, @rw6+d8 movea rw3, @rw7+d8 movea rw3, @rw0+d16 movea rw3, @rw1+d16 movea rw3, @rw2+d16 movea rw3, @rw3+d16 movea rw3, @rw0+rw7 movea rw3, @rw1+rw7 movea rw3, @pc+d16 movea rw3, addr16 movea rw4, @rw0+d8 movea rw4, @rw1+d8 movea rw4, @rw2+d8 movea rw4, @rw3+d8 movea rw4, @rw4+d8 movea rw4, @rw5+d8 movea rw4, @rw6+d8 movea rw4, @rw7+d8 movea rw4, @rw0+d16 movea rw4, @rw1+d16 movea rw4, @rw2+d16 movea rw4, @rw3+d16 movea rw4, @rw0+rw7 movea rw4, @rw1+rw7 movea rw4, @pc+d16 movea rw4, addr16 movea rw5, @rw0+d8 movea rw5, @rw1+d8 movea rw5, @rw2+d8 movea rw5, @rw3+d8 movea rw5, @rw4+d8 movea rw5, @rw5+d8 movea rw5, @rw6+d8 movea rw5, @rw7+d8 movea rw5, @rw0+d16 movea rw5, @rw1+d16 movea rw5, @rw2+d16 movea rw5, @rw3+d16 movea rw5, @rw0+rw7 movea rw5, @rw1+rw7 movea rw5, @pc+d16 movea rw5, addr16 movea rw6 ,@rw0+d8 movea rw6 ,@rw1+d8 movea rw6 ,@rw2+d8 movea rw6 ,@rw3+d8 movea rw6 ,@rw4+d8 movea rw6 ,@rw5+d8 movea rw6 ,@rw6+d8 movea rw6 ,@rw7+d8 movea rw6 ,@rw0+d16 movea rw6 ,@rw1+d16 movea rw6 ,@rw2+d16 movea rw6 ,@rw3+d16 movea rw6 ,@rw0+rw7 movea rw6 ,@rw1+rw7 movea rw6 ,@pc+d16 movea rw6 ,addr16 movea rw7, @rw0+d8 movea rw7, @rw1+d8 movea rw7, @rw2+d8 movea rw7, @rw3+d8 movea rw7, @rw4+d8 movea rw7, @rw5+d8 movea rw7, @rw6+d8 movea rw7, @rw7+d8 movea rw7, @rw0+d16 movea rw7, @rw1+d16 movea rw7, @rw2+d16 movea rw7, @rw3+d16 movea rw7, @rw0+rw7 movea rw7, @rw1+rw7 movea rw7, @pc+d16 movea rw7, addr16 @pc+d16 b.3 instruction map 350 appendix b: instructions MB90580 series table b.3.1o mov ri, ea (first byte = 7a h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 mov r0, r0 mov r0, r1 mov r0, r2 mov r0, r3 mov r0, r4 mov r0, r5 mov r0, r6 mov r0, r7 mov r0, @rw0 mov r0, @rw1 mov r0, @rw2 mov r0, @rw3 mov r0, @rw0+ mov r0, @rw1+ mov r0, @rw2+ mov r0, @rw3+ mov r0, @rw0+d8 mov r0, @rw1+d8 mov r0, @rw2+d8 mov r0, @rw3+d8 mov r0, @rw4+d8 mov r0, @rw5+d8 mov r0, @rw6+d8 mov r0, @rw7+d8 mov r0, @rw0+d16 mov r0, @rw1+d16 mov r0, @rw2+d16 mov r0, @rw3+d16 mov r0, @rw0+rw7 mov r0, @rw1+rw7 mov r0, @pc+d16 mov r0, @addr16 mov r1, r0 mov r1, r1 mov r1, r2 mov r1, r3 mov r1, r4 mov r1, r5 mov r1, r6 mov r1, r7 mov r1, @rw0 mov r1, @rw1 mov r1, @rw2 mov r1, @rw3 mov r1, r1, @rw0+ mov r1, r1, @rw1+ mov r1, r1, @rw2+ mov r1, r1, @rw3+ mov r2, r0 mov r2, r1 mov r2, r2 mov r2, r3 mov r2, r4 mov r2, r5 mov r2, r6 mov r2, r7 mov r2, @rw0 mov r2, @rw1 mov r2, @rw2 mov r2, @rw3 mov r2, @rw0+ mov r2, @rw1+ mov r2, @rw2+ mov r2, @rw3+ mov r3, r0 mov r3, r1 mov r3, r2 mov r3, r3 mov r3, r4 mov r3, r5 mov r3, r6 mov r3, r7 mov r3, @rw0 mov r3, @rw1 mov r3, @rw2 mov r3, @rw3 mov r3, @rw0+ mov r3, @rw1+ mov r3, @rw2+ mov r3, @rw3+ mov r4, r0 mov r4, r1 mov r4, r2 mov r4, r3 mov r4, r4 mov r4, r5 mov r4, r6 mov r4, r7 mov r4, @rw0 mov r4, @rw1 mov r4, @rw2 mov r4, @rw3 mov r4, @rw0+ mov r4, @rw1+ mov r4, @rw2+ mov r4, @rw3+ mov r5, r0 mov r5, r1 mov r5, r2 mov r5, r3 mov r5, r4 mov r5, r5 mov r5, r6 mov r5, r7 mov r5, @rw0 mov r5, @rw1 mov r5, @rw2 mov r5, @rw3 mov r5, @rw0+ mov r5, @rw1+ mov r5, @rw2+ mov r5, @rw3+ mov r6, r0 mov r6, r1 mov r6, r2 mov r6, r3 mov r6, r4 mov r6, r5 mov r6, r6 mov r6, r7 mov r6, @rw0 mov r6, @rw1 mov r6, @rw2 mov r6, @rw3 mov r6, @rw0+ mov r6, @rw1+ mov r6, @rw2+ mov r6, @rw3+ mov r7, r0 mov r7, r1 mov r7, r2 mov r7, r3 mov r7, r4 mov r7, r5 mov r7, r6 mov r7, r7 mov r7, @rw0 mov r7, @rw1 mov r7, @rw2 mov r7, @rw3 mov r7, @rw0+ mov r7, @rw1+ mov r7, @rw2+ mov r7, @rw3+ mov r1, @rw0+d8 mov r1, @rw1+d8 mov r1, @rw2+d8 mov r1, @rw3+d8 mov r1, @rw4+d8 mov r1, @rw5+d8 mov r1, @rw6+d8 mov r1, @rw7+d8 mov r1, @rw0+d16 mov r1, @rw1+d16 mov r1, @rw2+d16 mov r1, @rw3+d16 mov r1, @rw0+rw7 mov r1, @rw1+rw7 mov r1, mov r1, addr16 mov r2, @rw0+d8 mov r2, @rw1+d8 mov r2, @rw2+d8 mov r2, @rw3+d8 mov r2, @rw4+d8 mov r2, @rw5+d8 mov r2, @rw6+d8 mov r2, @rw7+d8 mov r2, @rw0+d16 mov r2, @rw1+d16 mov r2, @rw2+d16 mov r2, @rw3+d16 mov r2, @rw0+rw7 mov r2, @rw1+rw7 mov r2, @pc+d16 mov r2, addr16 mov r3, @rw0+d8 mov r3, @rw1+d8 mov r3, @rw2+d8 mov r3, @rw3+d8 mov r3, @rw4+d8 mov r3, @rw5+d8 mov r3, @rw6+d8 mov r3, @rw7+d8 mov r3, @rw0+d16 mov r3, @rw1+d16 mov r3, @rw2+d16 mov r3, @rw3+d16 mov r3, @rw0+rw7 mov r3, @rw1+rw7 mov r3, @pc+d16 mov r3, addr16 mov r4, @rw0+d8 mov r4, @rw1+d8 mov r4, @rw2+d8 mov r4, @rw3+d8 mov r4, @rw4+d8 mov r4, @rw5+d8 mov r4, @rw6+d8 mov r4, @rw7+d8 mov r4, @rw0+d16 mov r4, @rw1+d16 mov r4, @rw2+d16 mov r4, @rw3+d16 mov r4, @rw0+rw7 mov r4, @rw1+rw7 mov r4, @pc+d16 mov r4, addr16 mov r5, @rw0+d8 mov r5, @rw1+d8 mov r5, @rw2+d8 mov r5, @rw3+d8 mov r5, @rw4+d8 mov r5, @rw5+d8 mov r5, @rw6+d8 mov r5, @rw7+d8 mov r5, @rw0+d16 mov r5, @rw1+d16 mov r5, @rw2+d16 mov r5, @rw3+d16 mov r5, @rw0+rw7 mov r5, @rw1+rw7 mov r5, @pc+d16 mov r5, addr16 mov r6, @rw0+d8 mov r6, @rw1+d8 mov r6, @rw2+d8 mov r6, @rw3+d8 mov r6, @rw4+d8 mov r6, @rw5+d8 mov r6, @rw6+d8 mov r6, @rw7+d8 mov r6, @rw0+d16 mov r6, @rw1+d16 mov r6, @rw2+d16 mov r6, @rw3+d16 mov r6, @rw0+rw7 mov r6, @rw1+rw7 mov r6, @pc+d16 mov r6, addr16 mov r7, @rw0+d8 mov r7, @rw1+d8 mov r7, @rw2+d8 mov r7, @rw3+d8 mov r7, @rw4+d8 mov r7, @rw5+d8 mov r7, @rw6+d8 mov r7, @rw7+d8 mov r7, @rw0+d16 mov r7, @rw1+d16 mov r7, @rw2+d16 mov r7, @rw3+d16 mov r7, @rw0+rw7 mov r7, @rw1+rw7 mov r7, @pc+d16 mov r7, addr16 @pc+d16 b.3 instruction map MB90580 series appendix b: instructions 351 table b.3.1p movw rwi, ea (first byte = 7b h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 movw rw0, rw0 movw rw0, rw1 movw rw0, rw2 movw rw0, rw3 movw rw0, rw4 movw rw0, rw5 movw rw0, rw6 movw rw0, rw7 movw rw0, @rw0 movw rw0, @rw1 movw rw0, @rw2 movw rw0, @rw3 movw r w0, @rw0+ movw r w0, @rw1+ movw r w0, @rw2+ movw r w0, @rw3+ movw rw0, @rw0+d8 movw rw0, @rw1+d8 movw rw0, @rw2+d8 movw rw0, @rw3+d8 movw rw0, @rw4+d8 movw rw0, @rw5+d8 movw rw0, @rw6+d8 movw rw0, @rw7+d8 movw rw0, @rw0+d16 movw rw0, @rw1+d16 movw rw0, @rw2+d16 movw rw0, @rw3+d16 movw rw0, @rw0+rw7 movw rw0, @rw1+rw7 movw rw0, @pc+d16 movw rw0, addr16 movw rw1, rw0 movw rw1, rw1 movw rw1, rw2 movw rw1, rw3 movw rw1, rw4 movw rw1, rw5 movw rw1, rw6 movw rw1, rw7 movw rw1, @rw0 movw rw1, @rw1 movw rw1, @rw2 movw rw1, @rw3 movw r w1, @rw0+ movw r w1, @rw1+ movw r w1, @rw2+ movw r w1, @rw3+ movw rw2, rw0 movw rw2, rw1 movw rw2, rw2 movw rw2, rw3 movw rw2, rw4 movw rw2, rw5 movw rw2, rw6 movw rw2, rw7 movw rw2, @rw0 movw rw2, @rw1 movw rw2, @rw2 movw rw2, @rw3 movw r w2, @rw0+ movw r w2, @rw1+ movw r w2, @rw2+ movw r w2, @rw3+ movw rw3, rw0 movw rw3, rw1 movw rw3, rw2 movw rw3, rw3 movw rw3, rw4 movw rw3, rw5 movw rw3, rw6 movw rw3, rw7 movw rw3, @rw0 movw rw3, @rw1 movw rw3, @rw2 movw rw3, @rw3 movw r w3, @rw0+ movw r w3, @rw1+ movw r w3, @rw2+ movw r w3, @rw3+ movw rw4, rw0 movw rw4, rw1 movw rw4, rw2 movw rw4, rw3 movw rw4, rw4 movw rw4, rw5 movw rw4, rw6 movw rw4, rw7 movw rw4, @rw0 movw rw4, @rw1 movw rw4, @rw2 movw rw4, @rw3 movw r w4, @rw0+ movw r w4, @rw1+ movw r w4, @rw2+ movw r w4, @rw3+ movw rw5, rw0 movw rw5, rw1 movw rw5, rw2 movw rw5, rw3 movw rw5, rw4 movw rw5, rw5 movw rw5, rw6 movw rw5, rw7 movw rw5, @rw0 movw rw5, @rw1 movw rw5, @rw2 movw rw5, @rw3 movw r w5, @rw0+ movw r w5, @rw1+ movw r w5, @rw2+ movw r w5, @rw3+ movw rw6, rw0 movw rw6, rw1 movw rw6, rw2 movw rw6, rw3 movw rw6, rw4 movw rw6, rw5 movw rw6, rw6 movw rw6, rw7 movw rw6, @rw0 movw rw6, @rw1 movw rw6, @rw2 movw rw6, @rw3 movw r w6, @rw0+ movw r w6, @rw1+ movw r w6, @rw2+ movw r w6, @rw3+ movw rw7, rw0 movw rw7, rw1 movw rw7, rw2 movw rw7, rw3 movw rw7, rw4 movw rw7, rw5 movw rw7, rw6 movw rw7, rw7 movw rw7, @rw0 movw rw7, @rw1 movw rw7, @rw2 movw rw7, @rw3 movw r w7, @rw0+ movw r w7, @rw1+ movw r w7, @rw2+ movw r w7, @rw3+ movw rw1, @rw0+d8 movw rw1, @rw1+d8 movw rw1, @rw2+d8 movw rw1, @rw3+d8 movw rw1, @rw4+d8 movw rw1, @rw5+d8 movw rw1, @rw6+d8 movw rw1, @rw7+d8 movw rw1, @rw0+d16 movw rw1, @rw1+d16 movw rw1, @rw2+d16 movw rw1, @rw3+d16 movw rw1, @rw0+rw7 movw rw1, @rw1+rw7 movw rw1, movw rw1, addr16 movw rw2, @rw0+d8 movw rw2, @rw1+d8 movw rw2, @rw2+d8 movw rw2, @rw3+d8 movw rw2, @rw4+d8 movw rw2, @rw5+d8 movw rw2, @rw6+d8 movw rw2, @rw7+d8 movw rw2, @rw0+d16 movw rw2, @rw1+d16 movw rw2, @rw2+d16 movw rw2, @rw3+d16 movw rw2, @rw0+rw7 movw rw2, @rw1+rw7 movw rw2, @pc+d16 movw rw2, addr16 movw rw3, @rw0+d8 movw rw3, @rw1+d8 movw rw3, @rw2+d8 movw rw3, @rw3+d8 movw rw3, @rw4+d8 movw rw3, @rw5+d8 movw rw3, @rw6+d8 movw rw3, @rw7+d8 movw rw3, @rw0+d16 movw rw3, @rw1+d16 movw rw3, @rw2+d16 movw rw3, @rw3+d16 movw rw3, @rw0+rw7 movw rw3, @rw1+rw7 movw rw3, @pc+d16 movw rw3, addr16 movw rw4, @rw0+d8 movw rw4, @rw1+d8 movw rw4, @rw2+d8 movw rw4, @rw3+d8 movw rw4, @rw4+d8 movw rw4, @rw5+d8 movw rw4, @rw6+d8 movw rw4, @rw7+d8 movw rw4, @rw0+d16 movw rw4, @rw1+d16 movw rw4, @rw2+d16 movw rw4, @rw3+d16 movw rw4, @rw0+rw7 movw rw4, @rw1+rw7 movw rw4, @pc+d16 movw rw4, addr16 movw rw5, @rw0+d8 movw rw5, @rw1+d8 movw rw5, @rw2+d8 movw rw5, @rw3+d8 movw rw5, @rw4+d8 movw rw5, @rw5+d8 movw rw5, @rw6+d8 movw rw5, @rw7+d8 movw rw5, @rw0+d16 movw rw5, @rw1+d16 movw rw5, @rw2+d16 movw rw5, @rw3+d16 movw rw5, @rw0+rw7 movw rw5, @rw1+rw7 movw rw5, @pc+d16 movw rw5, addr16 movw rw6, @rw0+d8 movw rw6, @rw1+d8 movw rw6, @rw2+d8 movw rw6, @rw3+d8 movw rw6, @rw4+d8 movw rw6, @rw5+d8 movw rw6, @rw6+d8 movw rw6, @rw7+d8 movw rw6, @rw0+d16 movw rw6, @rw1+d16 movw rw6, @rw2+d16 movw rw6, @rw3+d16 movw rw6, @rw0+rw7 movw rw6, @rw1+rw7 movw rw6, @pc+d16 movw rw6, addr16 movw rw7, @rw0+d8 movw rw7, @rw1+d8 movw rw7, @rw2+d8 movw rw7, @rw3+d8 movw rw7, @rw4+d8 movw rw7, @rw5+d8 movw rw7, @rw6+d8 movw rw7, @rw7+d8 movw rw7, @rw0+d16 movw rw7, @rw1+d16 movw rw7, @rw2+d16 movw rw7, @rw3+d16 movw rw7, @rw0+rw7 movw rw7, @rw1+rw7 movw rw7, @pc+d16 movw rw7, addr16 @pc+d16 b.3 instruction map 352 appendix b: instructions MB90580 series table b.3.1q mov ea, ri (first byte = 7c h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 mov r0, r0 mov r1, r0 mov r2, r0 mov r3, r0 mov r4, r0 mov r5, r0 mov r6, r0 mov r7, r0 mov @rw0, r0 mov @rw1, r0 mov @rw2, r0 mov @rw3, r0 mov @rw0+, r0 mov @rw1+, r0 mov @rw2+, r0 mov @rw3+, r0 mov @r w0+d8, r0 mov @r w1+d8, r0 mov @r w2+d8, r0 mov @r w3+d8, r0 mov @r w4+d8, r0 mov @r w5+d8, r0 mov @r w6+d8, r0 mov @r w7+d8, r0 mov @rw w0+d16, r0 mov @rw w1+d16, r0 mov @rw w2+d16, r0 mov @rw w3+d16, r0 mov @rw w0+rw7, r0 mov @rw w1+rw7, r0 mov pc+d16, r0 mov addr16, r0 mov r0, r1 mov r1, r1 mov r2, r1 mov r3, r1 mov r4, r1 mov r5, r1 mov r6, r1 mov r7, r1 mov @rw0, r1 mov @rw1, r1 mov @rw2, r1 mov @rw3, r1 mov @rw0+, r1 mov @rw1+, r1 mov @rw2+, r1 mov @rw3+, r1 mov r0, r2 mov r1, r2 mov r2, r2 mov r3, r2 mov r4, r2 mov r5, r2 mov r6, r2 mov r7, r2 mov @rw0, r2 mov @rw1, r2 mov @rw2, r2 mov @rw3, r2 mov @rw0+, r2 mov @rw1+, r2 mov @rw2+, r2 mov @rw3+, r2 mov r0, r3 mov r1, r3 mov r2, r3 mov r3, r3 mov r4, r3 mov r5, r3 mov r6, r3 mov r7, r3 mov @rw0, r3 mov @rw1, r3 mov @rw2, r3 mov @rw3, r3 mov @rw0+, r3 mov @rw1+, r3 mov @rw2+, r3 mov @rw3+, r3 mov r0, r4 mov r1, r4 mov r2, r4 mov r3, r4 mov r4, r4 mov r5, r4 mov r6, r4 mov r7, r4 mov @rw0, r4 mov @rw1, r4 mov @rw2, r4 mov @rw3, r4 mov @rw0+, r4 mov @rw1+, r4 mov @rw2+, r4 mov @rw3+, r4 mov r0, r5 mov r1, r5 mov r2, r5 mov r3, r5 mov r4, r5 mov r5, r5 mov r6, r5 mov r7, r5 mov @rw0, r5 mov @rw1, r5 mov @rw2, r5 mov @rw3, r5 mov @rw0+, r5 mov @rw1+, r5 mov @rw2+, r5 mov @rw3+, r5 mov r0, r6 mov r1, r6 mov r2, r6 mov r3, r6 mov r4, r6 mov r5, r6 mov r6, r6 mov r7, r6 mov @rw0, r6 mov @rw1, r6 mov @rw2, r6 mov @rw3, r6 mov @rw0+, r6 mov @rw1+, r6 mov @rw2+, r6 mov @rw3+, r6 mov r0, r7 mov r1, r7 mov r2, r7 mov r3, r7 mov r4, r7 mov r5, r7 mov r6, r7 mov r7, r7 mov @rw0, r7 mov @rw1, r7 mov @rw2, r7 mov @rw3, r7 mov @rw0+, r7 mov @rw1+, r7 mov @rw2+, r7 mov @rw3+, r7 mov @r w0+d8, r1 mov @r w1+d8, r1 mov @r w2+d8, r1 mov @r w3+d8, r1 mov @r w4+d8, r1 mov @r w5+d8, r1 mov @r w6+d8, r1 mov @r w7+d8, r1 mov @rw 0+d16, r1 mov @rw 1+d16, r1 mov @rw 2+d16, r1 mov @rw 3+d16, r1 mov @rw 0+rw7, r1 mov @rw 1+rw7, r1 mov mov addr16, r1 mov @r, w0+d8, r2 mov @r w1+d8, r2 mov @r w2+d8, r2 mov @r w3+d8, r2 mov @r w4+d8, r2 mov @r w5+d8, r2 mov @r w6+d8, r2 mov @r w7+d8, r2 mov @rw 0+d16, r2 mov @rw 1+d16, r2 mov @rw 2+d16, r2 mov @rw 3+d16, r2 mov @rw 0+rw7, r2 mov @rw 1+rw7, r2 mov pc+d16, r2 mov addr16, r2 mov @r w0+d8, r3 mov @r w1+d8, r3 mov @r w2+d8, r3 mov @r w3+d8, r3 mov @r w4+d8, r3 mov @r w5+d8, r3 mov @r w6+d8, r3 mov @r w7+d8, r3 mov @rw 0+d16, r3 mov @rw 1+d16, r3 mov @rw 2+d16, r3 mov @rw 3+d16, r3 mov @rw 0+rw7, r3 mov @rw 1+rw7, r3 mov pc+d16, r3 mov addr16, r3 mov @r w0+d8, r4 mov @r w1+d8, r4 mov @r, w2+d8, r4 mov @r, w3+d8, r4 mov @r w4+d8, r4 mov @r w5+d8, r4 mov @r w6+d8, r4 mov @r w7+d8, r4 mov @rw 0+d16, r4 mov @rw 1+d16, r4 mov @rw 2+d16, r4 mov @rw 3+d16, r4 mov @rw 0+rw7, r4 mov @rw 1+rw7, r4 mov pc+d16, r4 mov addr16, r4 mov @r w0+d8, r5 mov @r w1+d8, r5 mov @r w2+d8, r5 mov @r w3+d8, r5 mov @r w4+d8, r5 mov @r w5+d8, r5 mov @r w6+d8, r5 mov @r w7+d8, r5 mov @rw 0+d16, r5 mov @rw 1+d16, r5 mov @rw 2+d16, r5 mov @rw 3+d16, r5 mov @rw 0+rw7, r5 mov @rw 1+rw7, r5 mov pc+d16, r5 mov addr16, r5 mov @r w0+d8, r6 mov @r w1+d8, r6 mov @r w2+d8, r6 mov @r w3+d8, r6 mov @r w4+d8, r6 mov @r w5+d8, r6 mov @r w6+d8, r6 mov @r w7+d8, r6 mov @rw 0+d16, r6 mov @rw 1+d16, r6 mov @rw 2+d16, r6 mov @rw 3+d16, r6 mov @rw 0+rw7, r6 mov @rw 1+rw7,r6 mov pc+d16, r6 mov addr16, r6 mov @r w0+d8, r7 mov @r w1+d8, r7 mov @r w2+d8, r7 mov @r w3+d8, r7 mov @r w4+d8, r7 mov @r w5+d8, r7 mov @r w6+d8, r7 mov @r w7+d8, r7 mov @rw 0+d16, r7 mov @rw 1+d16, r7 mov @rw 2+d16, r7 mov @rw 3+d16, r7 mov @rw 0+rw7, r7 mov @rw 1+rw7, r7 mov pc+d16, r7 mov addr16, r7 pc+d16, r1 b.3 instruction map MB90580 series appendix b: instructions 353 table b.3.1r movw ea, rwi (first byte = 7d h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 movw rw0, rw0 movw rw1, rw0 movw rw2, rw0 movw rw3, rw0 movw rw4, rw0 movw rw5, rw0 movw rw6, rw0 movw rw7, rw0 movw @rw0, rw0 movw @rw1, rw0 movw @rw2, rw0 movw @rw3, rw0 movw @rw0+, rw0 movw @rw1+, rw0 movw @rw2+, rw0 movw @rw3+, rw0 movw @rw 0+d8, rw0 movw @rw 1+d8, rw0 movw @rw 2+d8, rw0 movw @rw 3+d8, rw0 movw @rw 4+d8, rw0 movw @rw 5+d8, rw0 movw @rw 6+d8, rw0 movw @rw 7+d8, rw0 movw@rw0 +d16, rw0 movw@rw1 +d16, rw0 movw@rw2 +d16, rw0 movw@rw3 +d16, rw0 movw@rw0 +rw7, rw0 movw@rw1 +rw7, rw0 movw @pc+ d16, rw0 movw addr 16, rw0 movw rw0, rw1 movw rw1, rw1 movw rw2, rw1 movw rw3, rw1 movw rw4, rw1 movw rw5, rw1 movw rw6, rw1 movw rw7, rw1 movw @rw0, rw1 movw @rw1, rw1 movw @rw2, rw1 movw @rw3, rw1 movw @ rw0+, rw1 movw @ rw1+, rw1 movw @ rw2+, rw1 movw @ rw3+, rw1 movw @rw 0+d8, rw1 movw @r 1+d8, rw1 movw @rw 2+d8, rw1 movw @rw 3+d8, rw1 movw @rw 4+d8, rw1 movw @rw 5+d8, rw1 movw @rw 6+d8, rw1 movw @rw 7+d8, rw1 movw@rw0 +d16, rw1 movw@rw1 +d16, rw1 movw@rw2 +d16, rw1 movw@rw3 +d16, rw1 movw@rw0 +rw7, rw1 movw@rw1 +rw7, rw1 movw @pc+ d16, rw1 movw addr 16, rw1 movw rw0, rw2 movw rw1, rw2 movw rw2, rw2 movw rw3, rw2 movw rw4, rw2 movw rw5, rw2 movw rw6, rw2 movw rw7, rw2 movw @rw0, rw2 movw @rw1, rw2 movw @rw2, rw2 movw @rw3, rw2 movw @ rw0+, rw2 movw @ rw1+, rw2 movw @ rw2+, rw2 movw @ rw3+, rw2 movw @rw 0+d8, rw2 movw @r 1+d8, rw2 movw @rw 2+d8, rw2 movw @rw 3+d8, rw2 movw @rw 4+d8, rw2 movw @rw 5+d8, rw2 movw @rw 6+d8, rw2 movw @rw 7+d8, rw2 movw@rw0 +d16, rw2 movw@rw1 +d16, rw2 movw@rw2 +d16, rw2 movw@rw3 +d16, rw2 movw@rw0 +rw7, rw2 movw@rw1 +rw7, rw2 movw @pc+ d16, rw2 movw addr 16, rw2 movw rw0, rw3 movw rw1, rw3 movw rw2, rw3 movw rw3, rw3 movw rw4, rw3 movw rw5, rw3 movw rw6, rw3 movw rw7, rw3 movw @rw0, rw3 movw @rw1, rw3 movw @rw2, rw3 movw @rw3, rw3 movw @ rw0+, rw3 movw @ rw1+, rw3 movw @ rw2+, rw3 movw @ rw3+, rw3 movw @rw 0+d8, rw3 movw @rw 1+d8, rw3 movw @rw 2+d8, rw3 movw @rw 3+d8, rw3 movw @rw 4+d8, rw3 movw @rw 5+d8, rw3 movw @rw 6+d8, rw3 movw @rw 7+d8, rw3 movw@rw0 +d16, rw3 movw@rw1 +d16, rw3 movw@rw2 +d16, rw3 movw@rw3 +d16, rw3 movw@rw0 +rw7, rw3 movw@rw1 +rw7, rw3 movw @pc+ d16, rw3 movw addr 16, rw3 movw rw0, rw4 movw rw1, rw4 movw rw2, rw4 movw rw3, rw4 movw rw4, rw4 movw rw5, rw4 movw rw6, rw4 movw rw7, rw4 movw @rw0, rw4 movw @rw1, rw4 movw @rw2, rw4 movw @rw3, rw4 movw @ rw0+, rw4 movw @ rw1+, rw4 movw @ rw2+, rw4 movw @ rw3+, rw4 movw @rw 0+d8, rw4 movw @rw 1+d8, rw4 movw @rw 2+d8, rw4 movw @rw 3+d8, rw4 movw @rw 4+d8, rw4 movw @rw 5+d8, rw4 movw @rw 6+d8, rw4 movw @rw 7+d8, rw4 movw@rw0 +d16, rw4 movw@rw1 +d16, rw4 movw@rw2 +d16, rw4 movw@rw3 +d16, rw4 movw@rw0 +rw7, rw4 movw@rw1 +rw7, rw4 movw @pc+ d16, rw4 movw addr 16, rw4 movw rw0, rw5 movw rw1, rw5 movw rw2, rw5 movw rw3, rw5 movw rw4, rw5 movw rw5, rw5 movw rw6, rw5 movw rw7, rw5 movw @rw0, rw5 movw @rw1, rw5 movw @rw2, rw5 movw @rw3, rw5 movw @ rw0+, rw5 movw @ rw1+, rw5 movw @ rw2+, rw5 movw @ rw3+, rw5 movw @rw 0+d8, rw5 movw @rw 1+d8, rw5 movw @rw 2+d8, rw5 movw @rw 3+d8, rw5 movw @rw 4+d8, rw5 movw @rw 5+d8, rw5 movw @rw 6+d8, rw5 movw @rw 7+d8, rw5 movw@rw0 +d16, rw5 movw@rw1 +d16, rw5 movw@rw2 +d16, rw5 movw@rw3 +d16, rw5 movw@rw0 +rw7, rw5 movw@rw1 +rw7, rw5 movw @pc+ d16, rw5 movw addr 16, rw5 movw rw0, rw6 movw rw1, rw6 movw rw2, rw6 movw rw3, rw6 movw rw4, rw6 movw rw5, rw6 movw rw6, rw6 movw rw7, rw6 movw @rw0, rw6 movw @rw1, rw6 movw @rw2, rw6 movw @rw3, rw6 movw @ rw0+, rw6 movw @ rw1+, rw6 movw @ rw2+, rw6 movw @ rw3+, rw6 movw @rw 0+d8, rw6 movw @rw 1+d8, rw6 movw @rw 2+d8, rw6 movw @rw 3+d8, rw6 movw @rw 4+d8, rw6 movw @rw 5+d8, rw6 movw @rw 6+d8, rw6 movw @rw 7+d8, rw6 movw@rw0 +d16, rw6 movw@rw1 +d16, rw6 movw@rw2 +d16, rw6 movw@rw3 +d16, rw6 movw@rw0 +rw7, rw6 movw@rw1 +rw7, rw6 movw @pc+ d16, rw6 movw addr 16, rw6 movw rw0, rw7 movw rw1, rw7 movw rw2, rw7 movw rw3, rw7 movw rw4, rw7 movw rw5, rw7 movw rw6, rw7 movw rw7, rw7 movw @rw0, rw7 movw @rw1, rw7 movw @rw2, rw7 movw @rw3, rw7 movw @ rw0+, rw7 movw @ rw1+, rw7 movw @ rw2+, rw7 movw @ rw3+, rw7 movw @rw 0+d8, rw7 movw @rw 1+d8, rw7 movw @rw 2+d8, rw7 movw @rw 3+d8, rw7 movw @rw 4+d8, rw7 movw @rw 5+d8, rw7 movw @rw 6+d8, rw7 movw @rw 7+d8, rw7 movw@rw0 +d16, rw7 movw@rw1 +d16, rw7 movw@rw2 +d16, rw7 movw@rw3 +d16, rw7 movw@rw0 +rw7, rw7 movw@rw1 +rw7, rw7 movw @pc+ d16, rw7 movw addr 16, rw7 b.3 instruction map 354 appendix b: instructions MB90580 series table b.3.1s ch ri, ea (first byte = 7e h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 xch r0, r0 xch r0, r1 xch r0, r2 xch r0, r3 xch r0, r4 xch r0, r5 xch r0, r6 xch r0, r7 xch r0, @rw0 xch r0, @rw1 xch r0, @rw2 xch r0, @rw3 xch r0, @rw0+ xch r0, @rw1+ xch r0, @rw2+ xch r0, @rw3+ xch r0, @rw0+d8 xch r0, @rw1+d8 xch r0, @rw2+d8 xch r0, @rw3+d8 xch r0, @rw4+d8 xch r0, @rw5+d8 xch r0, @rw6+d8 xch r0, @rw7+d8 xch r0, @rw0+d16 xch r0, @rw1+d16 xch r0, @rw2+d16 xch r0, @rw3+d16 xch r0, @rw0+rw7 xch r0, @rw1+rw7 xch r0, @pc+d16 xch r0, addr16 xch r1, r0 xch r1, r1 xch r1, r2 xch r1, r3 xch r1, r4 xch r1, r5 xch r1, r6 xch r1, r7 xch r1, @rw0 xch r1, @rw1 xch r1, @rw2 xch r1, @rw3 xch r1, @rw0+ xch r1, @rw1+ xch r1, @rw2+ xch r1, @rw3+ xch r2, r0 xch r2, r1 xch r2, r2 xch r2, r3 xch r2, r4 xch r2, r5 xch r2, r6 xch r2, r7 xch r2, @rw0 xch r2, @rw1 xch r2, @rw2 xch r2, @rw3 xch r2, @rw0+ xch r2, @rw1+ xch r2, @rw2+ xch r2, @rw3+ xch r3, r0 xch r3, r1 xch r3, r2 xch r3, r3 xch r3, r4 xch r3, r5 xch r3, r6 xch r3, r7 xch r3, @rw0 xch r3, @rw1 xch r3, @rw2 xch r3, @rw3 xch r3, @rw0+ xch r3, @rw1+ xch r3, @rw2+ xch r3, @rw3+ xch r4, r0 xch r4, r1 xch r4, r2 xch r4, r3 xch r4, r4 xch r4, r5 xch r4, r6 xch r4, r7 xch r4, @rw0 xch r4, @rw1 xch r4, @rw2 xch r4, @rw3 xch r4, @rw0+ xch r4, @rw1+ xch r4, @rw2+ xch r4, @rw3+ xch r5, r0 xch r5, r1 xch r5, r2 xch r5, r3 xch r5, r4 xch r5, r5 xch r5, r6 xch r5, r7 xch r5, @rw0 xch r5, @rw1 xch r5, @rw2 xch r5, @rw3 xch r5, @rw0+ xch r5, @rw1+ xch r5, @rw2+ xch r5, @rw3+ xch r6, r0 xch r6, r1 xch r6, r2 xch r6, r3 xch r6, r4 xch r6, r5 xch r6, r6 xch r6, r7 xch r6, @rw0 xch r6, @rw1 xch r6, @rw2 xch r6, @rw3 xch r6, @rw0+ xch r6, @rw1+ xch r6, @rw2+ xch r6, @rw3+ xch r7, r0 xch r7, r1 xch r7, r2 xch r7, r3 xch r7, r4 xch r7, r5 xch r7, r6 xch r7, r7 xch r7, @rw0 xch r7, @rw1 xch r7, @rw2 xch r7, @rw3 xch r7, @rw0+ xch r7, @rw1+ xch r7, @rw2+ xch r7, @rw3+ xch r1, @rw0+d8 xch r1, @rw1+d8 xch r1, @rw2+d8 xch r1, @rw3+d8 xch r1, @rw4+d8 xch r1, @rw5+d8 xch r1, @rw6+d8 xch r1, @rw7+d8 xch r1, @rw0+d16 xch r1, @rw1+d16 xch r1, @rw2+d16 xch r1, @rw3+d16 xch r1, @rw0+rw7 xch r1, @rw1+rw7 xch r1, xch r1, addr16 xch r2, @rw0+d8 xch r2, @rw1+d8 xch r2, @rw2+d8 xch r2, @rw3+d8 xch r2, @rw4+d8 xch r2, @rw5+d8 xch r2, @rw6+d8 xch r2, @rw7+d8 xch r2, @rw0+d16 xch r2, @rw1+d16 xch r2, @rw2+d16 xch r2, @rw3+d16 xch r2, @rw0+rw7 xch r2, @rw1+rw7 xch r2, @pc+d16 xch r2, addr16 xch r3, @rw0+d8 xch r3, @rw1+d8 xch r3, @rw2+d8 xch r3, @rw3+d8 xch r3, @rw4+d8 xch r3, @rw5+d8 xch r3, @rw6+d8 xch r3, @rw7+d8 xch r3, @rw0+d16 xch r3, @rw1+d16 xch r3, @rw2+d16 xch r3, @rw3+d16 xch r3, @rw0+rw7 xch r3, @rw1+rw7 xch r3, @pc+d16 xch r3, addr16 xch r4, @rw0+d8 xch r4, @rw1+d8 xch r4, @rw2+d8 xch r4, @rw3+d8 xch r4, @rw4+d8 xch r4, @rw5+d8 xch r4, @rw6+d8 xch r4, @rw7+d8 xch r4, @rw0+d16 xch r4, @rw1+d16 xch r4, @rw2+d16 xch r4, @rw3+d16 xch r4, @rw0+rw7 xch r4, @rw1+rw7 xch r4, @pc+d16 xch r4, addr16 xch r5, @rw0+d8 xch r5, @rw1+d8 xch r5, @rw2+d8 xch r5, @rw3+d8 xch r5, @rw4+d8 xch r5, @rw5+d8 xch r5, @rw6+d8 xch r5, @rw7+d8 xch r5, @rw0+d16 xch r5, @rw1+d16 xch r5, @rw2+d16 xch r5, @rw3+d16 xch r5, @rw0+rw7 xch r5, @rw1+rw7 xch r5, @pc+d16 xch r5, addr16 xch r6, @rw0+d8 xch r6, @rw1+d8 xch r6, @rw2+d8 xch r6, @rw3+d8 xch r6, @rw4+d8 xch r6, @rw5+d8 xch r6, @rw6+d8 xch r6, @rw7+d8 xch r6, @rw0+d16 xch r6, @rw1+d16 xch r6, @rw2+d16 xch r6, @rw3+d16 xch r6, @rw0+rw7 xch r6, @rw1+rw7 xch r6, @pc+d16 xch r6, addr16 xch r7, @rw0+d8 notw r7, @rw1+d8 xch r7, @rw2+d8 notw r7, @rw3+d8 notw r7, @rw4+d8 xch r7, @rw5+d8 xch r7, @rw6+d8 xch r7, @rw7+d8 xch r7, @rw0+d16 xch r7, @rw1+d16 xch r7, @rw2+d16 xch r7, @rw3+d16 xch r7, @rw0+rw7 xch r7, @rw1+rw7 xch r7, @pc+d16 xch r7, addr16 @pc+d16 b.3 instruction map MB90580 series appendix b: instructions 355 table b.3.1t xchw rwi, ea (first byte = 7f h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 xchw rw0, rw0 xchw rw0, rw1 xchw rw0, rw2 xchw rw0, rw3 xchw rw0, rw4 xchw rw0, rw5 xchw rw0, rw6 xchw rw0, rw7 xchw rw0, @rw0 xchw rw0, @rw1 xchw rw0, @rw2 xchw rw0, @rw3 xchw r w0, @rw0+ xchw r w0, @rw1+ xchw r w0, @rw2+ xchw r w0, @rw3+ xchw rw0, @rw0+d8 xchw rw0, @rw1+d8 xchw rw0, @rw2+d8 xchw rw0, @rw3+d8 xchw rw0, @rw4+d8 xchw rw0, @rw5+d8 xchw rw0, @rw6+d8 xchw rw0, @rw7+d8 xchw rw0, @rw0+d16 xchw rw0, @rw1+d16 xchw rw0, @rw2+d16 xchw rw0, @rw3+d16 xchw rw0, @rw0+rw7 xchw rw0, @rw1+rw7 xchw rw0, @pc +d16 xchw rw0, addr16 xchw rw1, rw0 xchw rw1, rw1 xchw rw1, rw2 xchw rw1, rw3 xchw rw1, rw4 xchw rw1, rw5 xchw rw1, rw6 xchw rw1, rw7 xchw rw1, @rw0 xchw rw1, @rw1 xchw rw1, @rw2 xchw rw1, @rw3 xchw r w1, @rw0+ xchw r w1, @rw1+ xchw r w1, @rw2+ xchw r w1, @rw3+ xchw rw2, rw0 xchw rw2, rw1 xchw rw2, rw2 xchw rw2, rw3 xchw rw2, rw4 xchw rw2, rw5 xchw rw2, rw6 xchw rw2, rw7 xchw rw2, @rw0 xchw rw2, @rw1 xchw rw2, @rw2 xchw rw2, @rw3 xchw r w2, @rw0+ xchw r w2, @rw1+ xchw r w2, @rw2+ xchw r w2, @rw3+ xchw rw3, rw0 xchw rw3, rw1 xchw rw3, rw2 xchw rw3, rw3 xchw rw3, rw4 xchw rw3, rw5 xchw rw3, rw6 xchw rw3, rw7 xchw rw3, @rw0 xchw rw3, @rw1 xchw rw3, @rw2 xchw rw3, @rw3 xchw r w3, @rw0+ xchw r w3, @rw1+ xchw r w3, @rw2+ xchw r w3, @rw3+ xchw rw4, rw0 xchw rw4, rw1 xchw rw4, rw2 xchw rw4, rw3 xchw rw4, rw4 xchw rw4, rw5 xchw rw4, rw6 xchw rw4, rw7 xchw rw4, @rw0 xchw rw4, @rw1 xchw rw4, @rw2 xchw rw4, @rw3 xchw r w4, @rw0+ xchw r w4, @rw1+ xchw r w4, @rw2+ xchw r w4, @rw3+ xchw rw5, rw0 xchw rw5, rw1 xchw rw5, rw2 xchw rw5, rw3 xchw rw5, rw4 xchw rw5, rw5 xchw rw5, rw6 xchw rw5, rw7 xchw rw5, @rw0 xchw rw5, @rw1 xchw rw5, @rw2 xchw rw5, @rw3 xchw r w5, @rw0+ xchw r w5, @rw1+ xchw r w5, @rw2+ xchw r w5, @rw3+ xchw rw6, rw0 xchw rw6, rw1 xchw rw6, rw2 xchw rw6, rw3 xchw rw6, rw4 xchw rw6, rw5 xchw rw6, rw6 xchw rw6, rw7 xchw rw6, @rw0 xchw rw6, @rw1 xchw rw6, @rw2 xchw rw6, @rw3 xchw r w6, @rw0+ xchw r w6, @rw1+ xchw r w6, @rw2+ xchw r w6, @rw3+ xchw rw7, rw0 xchw rw7, rw1 xchw rw7, rw2 xchw rw7, rw3 xchw rw7, rw4 xchw rw7, rw5 xchw rw7, rw6 xchw rw7, rw7 xchw rw7, @rw0 xchw rw7, @rw1 xchw rw7, @rw2 xchw rw7, @rw3 xchw r w7, @rw0+ xchw r w7, @rw1+ xchw r w7, @rw2+ xchw r w7, @rw3+ xchw rw1, @rw0+d8 xchw rw1, @rw1+d8 xchw rw1, @rw2+d8 xchw rw1, @rw3+d8 xchw rw1, @rw4+d8 xchw rw1, @rw5+d8 xchw rw1, @rw6+d8 xchw rw1, @rw7+d8 xchw rw1, @rw0+d16 xchw rw1, @rw1+d16 xchw rw1, @rw2+d16 xchw rw1, @rw3+d16 xchw rw1, @rw0+rw7 xchw rw1, @rw1+rw7 xchw rw1, xchw rw1, addr16 xchw rw2, @rw0+d8 xchw rw2, @rw1+d8 xchw rw2, @rw2+d8 xchw rw2, @rw3+d8 xchw rw2, @rw4+d8 xchw rw2, @rw5+d8 xchw rw2, @rw6+d8 xchw rw2, @rw7+d8 xchw rw2, @rw0+d16 xchw rw2, @rw1+d16 xchw rw2, @rw2+d16 xchw rw2, @rw3+d16 xchw rw2, @rw0+rw7 xchw rw2, @rw1+rw7 xchw rw2, @pc+d16 xchw rw2, addr16 xchw rw3, @rw0+d8 xchw rw3, @rw1+d8 xchw rw3, @rw2+d8 xchw rw3, @rw3+d8 xchw rw3, @rw4+d8 xchw rw3, @rw5+d8 xchw rw3, @rw6+d8 xchw rw3, @rw7+d8 xchw rw3, @rw0+d16 xchw rw3, @rw1+d16 xchw rw3, @rw2+d16 xchw rw3, @rw3+d16 xchw rw3, @rw0+rw7 xchw rw3, @rw1+rw7 xchw rw3, @pc+d16 xchw rw3, addr16 xchw rw4, @rw0+d8 xchw rw4, @rw1+d8 xchw rw4, @rw2+d8 xchw rw4, @rw3+d8 xchw rw4, @rw4+d8 xchw rw4, @rw5+d8 xchw rw4, @rw6+d8 xchw rw4, @rw7+d8 xchw rw4, @rw0+d16 xchw rw4, @rw1+d16 xchw rw4, @rw2+d16 xchw rw4, @rw3+d16 xchw rw4, @rw0+rw7 xchw rw4, @rw1+rw7 xchw rw4, @pc+d16 xchw rw4, addr16 xchw rw5, @rw0+d8 xchw rw5, @rw1+d8 xchw rw5, @rw2+d8 xchw rw5, @rw3+d8 xchw rw5, @rw4+d8 xchw rw5, @rw5+d8 xchw rw5, @rw6+d8 xchw rw5, @rw7+d8 xchw rw5, @rw0+d16 xchw rw5, @rw1+d16 xchw rw5, @rw2+d16 xchw rw5, @rw3+d16 xchw rw5, @rw0+rw7 xchw rw5, @rw1+rw7 xchw rw5, @pc+d16 xchw rw5, addr16 xchw rw6, @rw0+d8 xchw rw6, @rw1+d8 xchw rw6, @rw2+d8 xchw rw6, @rw3+d8 xchw rw6, @rw4+d8 xchw rw6, @rw5+d8 xchw rw6, @rw6+d8 xchw rw6, @rw7+d8 xchw rw6, @rw0+d16 xchw rw6, @rw1+d16 xchw rw6, @rw2+d16 xchw rw6, @rw3+d16 xchw rw6, @rw0+rw7 xchw rw6, @rw1+rw7 xchw rw6, @pc+d16 xchw rw6, addr16 xchw rw7, @rw0+d8 xchw rw7, @rw1+d8 xchw rw7, @rw2+d8 xchw rw7, @rw3+d8 xchw rw7, @rw4+d8 xchw rw7, @rw5+d8 xchw rw7, @rw6+d8 xchw rw7, @rw7+d8 xchw rw7, @rw0+d16 xchw rw7, @rw1+d16 xchw rw7, @rw2+d16 xchw rw7, @rw3+d16 xchw rw7, @rw0+rw7 xchw rw7, @rw1+rw7 xchw rw7, @pc+d16 xchw rw7, addr16 @pc+d16 appendix c: the flash memory in the mb90f583 c.1 outline there is a 1m-bit flash memory (128k word x 8/64k word x 16) located at the fe~ff bank of the cpu memory map in mb90f583. with the flash memory interface circuit, it is possible for read access from and program access to the cpu. programming or erasing the flash memory are done by the cpu operation instruction through the flash memory interface circuit. therefore, with proper cpu control software, it is possible re-programming the flash memory of on-board mb90f583. that means changing of the data in the flash memory of on-board mb90f583 can be done. ? features 128k word x 8/64k word x 16 bit (16k+8k+8k+32k+64k sector architecture) compatible with jedec standard command automatic algorithm (embedded tm algorithm: same as mbm29f400ta) - automatic program algorithm - automatic erase algorithm sector erase suspend/sector erase resume function available program/erase cycle completion can be detected by data polling, toggle bit and cpu interrupt sector erase function (any combination of sector) number of programming/erasing: 10,000 times (minimum) note: embedded tm algorithm is trademarks of advanced mirco device, inc. ? program/erase operation the flash memory of mb90f583 cannot be programmed and read in the same time. when programming or erasing the flash memory, the programming data will be copied to the ram first; and then executing programming or erasing the flash memory in the ram. this keeps programming and erasing the flash memory as simple as a writing operation. ?register reserved lpm1 lpm0 rdy 76 54 321 0 we inte flash control register (fmcs) address: 0000ae h read/write initial value bit number (r/w) (0) (w) (r/w) (0) fmcs rdyint (0) (r/w) (0) (r/w) (0) (w) (0) (w) (x) (r/w) (0) reserved c.2 sector structure of 1m bit flash memory 358 appendix c: the flash memory in the mb90f583 MB90580 series c.2 sector structure of 1m bit flash memory sector structure of 1m bit flash memory in mb90f583 is shown in figure c.2a. the address in the figure c.2a shows upper and lower address of each sector. when accessing from cpu, sa0 is set in the fe bank register and sa1~4 are set in the ff bank register. figure c.2a sector structure of 1m bit flash memory flash memory sa4 (16k bytes) sa3 (8k bytes) sa2 (8k bytes) sa1 (32k bytes) sa0 (64k bytes) ffffff h ffc0000 h ffbffff h ff9ffff h ffa0000 h ff7ffff h ff80000 h feffff h ff00000 h feffff h 7fffff h 7fc0000 h 7fbffff h 7f9ffff h 7fa0000 h 7f7ffff h 7f80000 h 7effff h 7f00000 h 7effff h *programmer address: the programmer address is equivalent to the cpu address map where data is programmed to or erased from flash memory by the parallel writer (minato elec- tronic: model 1890a). when programmed to or erased from the flash memory by a general-purpose programmer, this address is needed to specified. cpu address programmer address* c.3 flash control register (fmcs) MB90580 series appendix c: the flash memory in the mb90f583 359 c.3 flash control register (fmcs) flash control register (fmcs) is a register which is used during programming or erasing the flash memory. [bit 7] inte (interrupt enable) this bit is used to enable an interrupt to the cpu when the operation of programming/erasing the flash memory is completed. an interrupt to the cpu will be generated when the inte bit is 1 and the rdyint bit is a 1. when the inte bit is 0, an interrupt will not be generated. [bit 6] rdyint (ready interrupt) this bit is used to show the programming/erasing operation status of the flash memory. this bit will be set to 1 when the flash memory program/erase cycle is completed. after flash memory program/erase cycle is completed and the bit is still 0, programing/erasing the flash memory is not allowed. only when this bit is changed to 1, programming/erasing the flash memory is allowed. writing 0 will clear this bit to 0 and writing 1 to this bit will be ignored. when automatic algorithm (refer to section c.4, automatic algorithm initiation method) is completed, this bit will be set to 1. 1 is always read when read modify write (rwm) is operated. [bit 5] we (write enable) this bit is write enable for the flash memory. when this bit is set to 1, the flash memory can be programed/erased right after the command sequence to fe~ff bank is issued. furthermore, this bit is used to start the command for programming/erasing the flash memory. it is recommended to always keep this bit set to 0, so that the flash memory will not be programmed or erased accidentally. inte interrupt enable 0 interrupt enable when program/erase cycle is completed 1 interrupt disable when program/erase cycle is completed rdyint ready interrupt 0 programming/erasing operation is on-going 1 programming/erasing operation is completed (interrupt request generated) we write enable 0 disable programming/erasing flash memory 1 enable programming/erasing flash memory reserved lpm1 lpm0 rdy 76 54 321 0 we inte flash control register (fmcs) address: 0000ae h read/write initial value bit number (r/w) (0) (w) (r/w) (0) fmcs rdyint (0) (r/w) (0) (r/w) (0) (w) (0) (w) (x) (r/w) (0) reserved c.3 flash control register (fmcs) 360 appendix c: the flash memory in the mb90f583 MB90580 series [bit 4] rdy (ready) this bit is used to indicate whether the flash memory is ready for programming/erasing. when this bit is set to 0, programming or erasing the flash memory is not allowed. however, it is possible to issue read/reset command and sector erase suspend command when this bit is 0. [bit 3] reserved bit this bit is reserved. it is recommended to always set this bit to 0 during normal operation. [bit 0] reserved bit this bit is reserved. it is recommended to always set this bit to 0 during normal operation. [bit 2, 0] lpm1, lpm0 (low power mode) when accessing flash memory, these two bits are used to control the power consumption of the flash memory. this bit cannot be set to 00. after reset, these bit must be set to 01, 10 or 11. since the flash memory access time by the cpu will be changed according to the frequency of the operating clock, it is recommended to set these bit according to the operating clock frequency of the cpu. note: rdyint bit and rdy bit cannot be changed in the same time. either one of these two bits should be changed when writing the control software. figure c.3a timing of rdyint and rdy rdy ready 0 programming/erasing is operating 1 programming/erasing is completed (next data programming/erasing is enabled. lmp0 lmp1 low power mode 00 initial value (access prohibited) 01 low power mode (internal operation frequency < 4 mhz) 10 low power mode (internal operation frequency < 8 mhz) 11 low power mode (internal operation frequency < 16 mhz) 1 machine cycle automatic program algorithm is completed rdyint bit rdy bit c.4 automatic algorithm initiation method MB90580 series appendix c: the flash memory in the mb90f583 361 c.4 automatic algorithm initiation method to start the automatic algorithm in the flash memory, there are five types of commands, 2 types of read/reset, programming, chip erase and sector erase. for sector erase, there are the sector erase suspend and the sector erase resume command. table c.4a shows the commands used during programming/erasing the flash memory. although the data shown in the command are all in byte, it is necessary to use word access to write the data. at this time, the upper byte of the data will be ignored. note: the address fx in table c.4a is either fe or ff for mb90f583. when using above commands, the accessible bank value for the device must be used to replaced fx the address found in the table c.4a is corresponding to the cpu memory address. all address and data written in hexadecimal and x is arbitrary value. ra: read address pa: program address , only even number address can be selected sa: sector address, refer to section c.2, sector structure of 1m bit flash memory. rd: read data pd: program data, only word data can be selected * : the 2 types of read/reset command can be reset the flash memory to read mode. table c.4a command sequence definitions command sequence bus write cycle reqd 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr data addr data addr data addr data addr data addr data read/reset* 1 fxxxxx xxf0 read/reset* 3 fxaaaa xxaa fx5554 xx55 fxaaaa xxf0 ra rd programming 4 fxaaaa xxaa fx5554 xx55 fxaaaa xxa0 pa (even) pd (word) chip erase 6 fxaaaa xxaa fx5554 xx55 fxaaaa xx80 fxaaaa xxaa fx5554 xx55 fxaaaa xx10 sector erase 6 fxaaaa xxaa fx5554 xx55 fxaaaa xx80 fxaaaa xxaa fx5554 xx55 sa (even) xx30 sector erase suspend sector erase is suspend by inputting the address fxxxxx, data xxb0 h sector erase resume sector erase is resumed by inputting the address fxxxxx, data xx30 h c.5 execution status of automatic algorithm in the flash memory, the programming or erasing can be done by automatic algorithm, so that there is a hardware sequence flag in the flash memory, which indicates the operation status and the operation completion. in the automatic algorithm, internal flash memory operation status can be checked by the hardware sequence flag which will be discussed in this section. ? hardware sequence flag hardware sequence flag consists of 4 flags, dq7 (data polling flag), dq6 (toggle bit flag), dq5 (exceeded timing limits flag) and dq3 (sector erase timer flag). these flag are used to check whether the programming or erasing the flash memory is completed and whether erase code are valid. hardware sequence flag is a checking point when performing read access to the address of the sector in the flash memory and after issuing the command sequence (see table c.4a). table c.5a shows the bit assignment of the hardware sequence flag. to check whether the automatic program/erase algorithm is under processing, it can be determined by either checking the hardware sequence flag or rdy bit of the flash control register (fmcs). after programming/erasing operation is completed, the flash memory will return to read/reset status. when making a control software, it is necessary to check the automatic program/erase algorithm completion by either the hardware sequence flag or rdy bit of the flash control register (fmcs) before going to other process such as reading data. it is also possible to check the next and the following sector erase code issued is valid by the hardware sequence flag. table c.5b shows the function of each hardware sequence flag. table c.5a hardware sequence flags bit assignment bit number 76543210 hardware sequence flag dq7 dq6 dq5 dq3 table c.5b hardware sequence flag status dq7 dq6 dq5 dq3 status change in normal operation programming ? programming complete (when program address is indicated) dq7 ? data:7 toggle ? data:6 0 ? data:5 0 ? data:3 chip/sector erase ? erase is completed 0 ? 1 toggle ? stop 0 ? 11 sector erase wait ? erase start 0 toggle 0 ? 11 sector erase ? sector erase suspend (sector being erased) 0 ? 1 toggle ? 10 1 ? 0 sector erase suspend ? sector erase resume (sector being erased) 1 ? 01 ? toggle 0 0 ? 1 sector erase suspend is in progress (sector not being erased) data:7 data:6 data:5 data:3 abnormal operation programming operation dq7 toggle 1 0 chip/sector erase 0 toggle 1 1 c.5 execution status of automatic algorithm MB90580 series appendix c: the flash memory in the mb90f583 363 c.5.1 data polling flag (dq7) data polling flag is used to indicate whether the automatic algorithm is executing or completed by using data polling function. table c.5.1a shows the status change of the data polling flag. ? programming during automatic program algorithm is executing, an attempt to read the flash memory will output the complement of the last written data to dq7, rather than the value at the address specified by the current address signal. ? chip/sector erase during chip erase/sector erase operation is in progress, an attempt to read the flash memory will output 0 to dq7. upon completion of chip erase/sector erase, an attempt to read the flash memory will output 1 to dq7. ? sector erase suspend during sector erase suspend is in progress, an attempt to read the flash memory will output 1 to dq7, if the address is within the sector which is being erased. if the address is not within the sector being erased, the flash memory will output bit 7 (data:7) of the read value of the address which is pointed. by looking at the toggle bit flag (dq6) together, it is possible to know whether the present sector is in sector erase suspend mode, or to know which sector is being erased. note: an attempt to read access to the address where automatic algorithm is starting will be ignored. after receiving the completion status of data polling flag (dq7), an attempt to read access will be allowed. hence, a read access from automatic algorithm completion should be done after the read access of the data polling completion. table c.5.1a status change of data polling flag (dq7) ? status change in normal operation operation status programming ? complete chip/sector erase ? complete sector erase wait ? start sector erase ? suspend (sector being erased) sector erase suspend ? resume (sector being erased) sector erase being suspended (sector not being erased) dq7 dq7 ? data:7 0 ? 10 0 ? 11 ? 0 data:7 ? status change in abnormal operation operation status programming operation chip/sector erase operation dq7 dq7 0 c.5 execution status of automatic algorithm 364 appendix c: the flash memory in the mb90f583 MB90580 series c.5.2 toggle bit flag (dq6) toggle bit flag is used to indicate whether the automatic algorithm is in progress or is completed by using toggle bit function. table c.5.2a shows status change of the toggle bit flag. ? programming, chip and sector erase during automatic program or erase algorithm, successive attempts to read access to the flash memory will result in toggling dq6 between 1 and 0. when automatic program algorithm and automatic chip/sector erase algorithm is completed and continuous read access is attempted, the flash memory will stop the dq6 toggling and output the value of bit 6 of the address specified by the current address signals. ? sector erase suspend when an attempt to read access in sector erase suspend mode, read value will be 1 if the address is specified within the sector being sector erased. if the specified address is not within to the sector being sector erased, the flash memory will output the value of bit 6 of the address specified by the current address signals. note: in programming operation, if the sector to be programmed is write-protected, the dq6 will be tog- gled for about 2 m s and then stop toggling without having the data change. in erasing operation, if all sectors are write-protected, the dq6 will be toggled for about 100 m s and then go back into read/reset mode without having the data change. table c.5.2a status change of toggle bit flag (dq6) ? status change in normal operation operation status programming ? complete chip/sector erase ? complete sector erase wait ? start sector erase ? suspend (sector being erased) sector erase suspend ? resume (sector being erased) sector erase being suspended (sector not being erased) dq6 toggle ? data:6 toggle ? stop toggle toggle ? 11 ? toggle data:6 ? status change in abnormal operation operation status programming operation chip/sector erase operation dq6 toggle toggle c.5 execution status of automatic algorithm MB90580 series appendix c: the flash memory in the mb90f583 365 c.5.3 exceeded timing limits flag (dq5) exceeded timing limits flag is used to indicate whether automatic algorithm has executed beyond the time (internal pulse count) specified in the flash memory. table c.5.3a shows status change of the exceeded timing limits flag. ? programming, chip and sector erase an attempt to read access after programming or chip/sector erase operation will output 0 to dq5 if automatic algorithm has executed within the time (internal pulse count) specified in the flash memory. if it is beyond the limit, 1 will be output to dq5. with irrespective of he automatic algorithm operation status, it is used to determine whether the program/erase operation has suceeded. thus, when 1 is read, it shows that programming or erasing operation is failed if automatic algorithm is regarded as still being executed by data polling function or toggle bit function. for an example, if the user tries to write 1 to the flash memory address where 0 is written, a failure will occur. in this case, flash memory will be locked and automatic algorithm will not be completed. consequently, valid data will not be outputted from the data polling flag (dq7). in the case of toggle bit flag (dq6), the toggle operation on bit 6 will not stopped and bit 5 output 1 to the exceeded timing limits flag (dq5). it means that the flash memory is not defective and it has been used incorrectly. the operation will return to normal after executing a reset command. table c.5.3a status change of exceeded timing limits flag (dq5) ? status change in normal operation operation status programming ? complete chip/sector erase ? complete sector erase wait ? start sector erase ? suspend (sector being erased) sector erase suspend ? resume (sector being erased) sector erase being suspended (sector not being erased) dq5 0 ? data5 0 ? 1 0 0 0 data:5 ? status change in abnormal operation operation status programming operation chip/sector erase operation dq5 11 c.5 execution status of automatic algorithm 366 appendix c: the flash memory in the mb90f583 MB90580 series c.5.4 sector erase timer flag (dq3) sector erase timer flag is used to indicate whether the automatic algorithm is executed beyond the sector erase wait time after the sector erase command is issued. table c.5.4a shows status change of the sector erase timer flag. ? during sector erase operation an attempt to read access after sector erase command is issued will output 0 to dq3 if automatic algorithm is executed within the sector erase wait time. 1 will be output to dq3 if the automatic algo- rithm is executed beyond the sector erase wait time. if the data polling flag or toggle bit flag indicates that the automatic erase algorithm is operating and dq3 is 1, internally controlled erasing is started. attempts to issue erase code and command other than sector erase suspend to the sector will be ignored until the erasing is completed. when dq3 is 0, issuing the additional sector erase code will be accepted. to ensure the command has been accepted, the control software should check the status of dq3 prior to each subsequent sector erase command. if dq3 was 1 on the status checking, the command may not be accepted. ? during sector erase suspend when read accessing during sector erase suspend, 1 will be output to dq3 if the specified address is within the sector which is being erased. if it does not within the sector being erased, the flash memory will output the value of bit 3 (data:3) at the address specified by the current address signals. table c.5.4a status change of sector erase timer flag (dq3) ? status change in normal operation operation status programming ? complete chip/sector erase ? complete sector erase wait ? start sector erase ? suspend (sector being erased) sector erase suspend ? resume (sector being erased) sector erase being suspended (sector not being erased) dq3 0 ? data:3 1 0 ? 11 ? 00 ? 1 data:3 ? status change in abnormal operation operation status programming operation chip/sector erase operation dq3 01 c.6 details of flash memory programming/erasing MB90580 series appendix c: the flash memory in the mb90f583 367 c.6 details of flash memory programming/erasing this section describes the following: command generated for initiating automatic algorithm, read/reset of flash memory, programming, chip erase, sector erase suspend and sector erase resume. flash memory can execute automatic algorithm when repeating the bus write cycle in read/reset, pro- gramming, chip erase, sector erase, sector erase suspend and sector erase resume command sequence. the bus write cycle must be sent continuously. completion of the automatic algorithm can be determined by checking the hardware sequence flag such as data polling function. if it is completed correctly, the flash memory will return to read/reset status. c.6.1 read/reset status this section describes how to isssue read/reset command to make flash memory returning to read/reset status. to make the flash memory returning to read/reset status, the command sequence of the read/reset command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and it needs to be continuously sent to the target sector in the flash memory. there are two kinds of bus write cycles in read/reset command, 1 and 3 bus write cycles, but there are no significant difference between them. since read/reset is the initial state, the flash memory will always go to this state when power-on and any command is correctly implemented. read/reset status is a waiting state for other command. normal read access can be done in the read/reset status. programming access is possible from the cpu. this command is not necessary for reading data in normal read access. this command is used when the operation is not completed correctly for some reasons, or when automatic algorithm needs to be reseted. c.6 details of flash memory programming/erasing 368 appendix c: the flash memory in the mb90f583 MB90580 series c.6.2 data programming this section will describe how to issue the programming command to program the flash memory. to initiate automatic program algorithm in the flash memory, the programming command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and it needs to be sent continuously to the target sector in the flash memory. automatic algorithm will be initiated and automatic programming will start when data programming to the target address is completed at the 4th cycle. ? specifying address specified programming address must be even number. it is not possible to program correctly on odd numbered addresses, so that it is necessary to program by word data unit with the even numbered address. programming can be done in any address and can go over sector boundary. however, only one word can be programmed with a single programming command. ? precautions on data programming it is impossible to program data from "1" to "0". when programming data from "1" to "0", data polling function (dq7) and toggle bit function (dq6) will not be completed. in this case, either the flash memory is considered to have error and programming timing limit will exceed making the exceeded timing limits flag (dq5) to output an error, or "1" will be assumed to have been programmed. when reading data in the read/reset status, the data remains "0". only erase operation can change data from "0" to "1". while automatic programming the flash memory is under processing, all other command will be ignored. if hardware reset is initiated during programming, take a good care on it. it is because the data being programmed to the address will not be guaranteed. ? data programming procedure figure c.6.2a shows the example procedure of programming the flash memory. by checking the hardware sequence flag (refer to section c.5, execution status of automatic algorithm), the status of automatic algorithm in flash memory can be determined. data polling flag (dq7) is used to check whether programming is completed. the data read from dq7 is the data found in the next programming address. it is necessary to re-check the data polling flag bit (dq7) even if the exceeded timing limits flag (dq5) is "1". it is because data polling flag (dq7) and the exceed time limit flag (dq5) will change in the same time. furthermore, it is not need to re-check the toggle bit flag(dq6) since it will stop at the same time when exceeded timing limits flag (dq5) changes to "1". c.6 details of flash memory programming/erasing MB90580 series appendix c: the flash memory in the mb90f583 369 figure c.6.2a example procedure of programming the flash memory start enable flash memory write fmcs:we (bit 5) write command sequence (1) fxaaaa ? xxaa (2) fx5555 ? xx55 (3) fxaaaa ? xxa0 (4) write addr ? write data internal address read data polling (dq7) time limits (dq5) internal address read last address data polling (dq7) disable flash memory write fmcs:we (bit 5) next address stop error no yes data data 0 1 data data checking hardware sequence flag c.6 details of flash memory programming/erasing 370 appendix c: the flash memory in the mb90f583 MB90580 series c.6.3 chip erase this section will describe how to issue the chip erase command to erase the whole chip. to erase all data from the flash memory, the chip erase command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and needs to be send continuously to the target address in the flash memory. chip erase command is executed by six bus write cycles. chip erase operation will start after 6th bus write cycle is finished. it is no necessary for the user to program the flash memory before erasing the chip. during automatic erase algorithm execution, flash memory will automatically write "0" to all bits before chip erase is operated. c.6.4 sector erase this section will describe how to issue the sector erase command to erase any sector in the flash memory. single sector or multiple sector can be erased in the same time. to erase a sector in the flash memory, the sector erase command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and needs to be sent continuously to the target sector in the flash memory. ? specifying sector sector erase command is executed by six bus write cycles. 50 m s of sector erase wait time will be started after issuing sector erase code (30h) to the accessible even numbered address of the sector in the 6th bus write cycle. when erasing several sectors in the same time, the erase code (30h) to the address of sectors to be erased needs to be issued. ? precautions on specifying multiple sectors sector erase operation will be started when the 50 m s of sector erase wait time is completed after the last sector erase code is issued. when erasing several sectors, it is necessary to input the address and the erase code of the following sector to erase in the 50 m s of sector erase wait time. however, the sector erase operation may not be accepted even after this wait time. it is necessary to check the sec- tor erase timer flag (dq3) to ensure whether the sector erase code issued was valid. at this time, the address to read the sector erase timer flag (dq3) should be specified to the sector to be erased. ? sector erase procedure by checking hardware sequence flag, the status of automatic algorithm in flash memory can be determined (refer to 1.5 automatic algorithm execution status). figure c.6.4a shows the example procedure of sector erase in the flash memory. in this example procedure, the toggle bit flag (dq6) is used to check erase completion take note that the data read for dq6 is the data in the sector that will be erased. it is not necessary to check the data polling flag (dq7) even if the exceeded timing limits flag (dq5) is "1". it is because data polling flag (dq7) will change at the same time the exceed timing limits flag (dq5) is changed. furthermore, it is necessary to re-check the toggle bit flag (dq6) since it will stop at the same time exceeded timing limits flag (dq5) changes to "1". c.6 details of flash memory programming/erasing MB90580 series appendix c: the flash memory in the mb90f583 371 figure c.6.4a example flowchart of erasing flash memory start enable flash memory erase fmcs:we (bit 5) erase command sequence (1) fxaaaa ? xxaa (2) fx5555 ? xx55 (3) fxaaaa ? xx80 (4) fx5554 ? xx55 (5) sector addr ? erase code (30h) internal address read 1 internal address read 2 toggle bit (dq6) data1 (dq6) = data2 (dq6) time limits flag (dq5) last sector disable flash memory erase fmcs:we (bit 5) next sector finish error no yes 0 1 no yes checking hardware sequence flag (6) input code to erase sector (30h) sector erase time (dq3) internal address read any other erase sector no yes internal address read 1 internal address read 2 toggle bit (dq6) data1 (dq6) = data2 (dq6) no yes 0 1 c.6 details of flash memory programming/erasing 372 appendix c: the flash memory in the mb90f583 MB90580 series c.6.5 suspend sector erase this section will describe how to issue the sector erase suspend command to suspend sector erase operation in the flash memory. during sector erase, it is possible to read data from the sector which is not being erased. to suspend sector erase in flash memory, the sector erase suspend command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and needs to be sent continuously to the target sector in the flash memory. during sector erase suspend command is executing, it is possible to read data from the sector that is not being erased. this enables only reading from the sector but it is not possible to programming the sector. this command is valid only during sector erasing time including the erase wait time, however, this command will be ignored when chip erase is operating or programming is operated. it will be implemented by issuing erase suspend code (b0h) to the flash memory. the address will be specified to any address within the flash memory. sector erase suspend command will be ignored during another erase suspend command. if the sector erase suspend command is issued during sector erase wait, sector erase wait will be ended suddenly and sector erase will be suspended. if sector erase suspend command is issued when sector erase is operating after sector erase wait, it will go to sector erase suspend status after maximum of 15 m s. c.6.6 resume sector erase this section will describe how to issue the sector erase resume command to restart the suspended sector erase in the flash memory. to restart the suspended sector erase, the sector erase resume command found in command sequence table (refer to section c.4, automatic algorithm initiation method, table c.4a) can be used and needs to be sent continuously to the target sector in the flash memory. sector erase resume command is used to restart the sector erase operation form sector erase suspend status. it will be implemented by issuing the sector erase resume code (30h) to the flash memory. the address can be specified to any address within the flash memory. sector erase resume command will be ignored during sector erase is operating. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9806 ? fujitsu limited printed in japan known bugs in hm MB90580 1. chapter 20.4.5 output compare unit ===================================== the documentation refers to outputs out0/1 and out2/3. there does not exist out2 and out3 ( see pinning). so compare register 0 corresponds to out0 only and compare register 1 to out1. last updated : 05-03-98 tka |
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